Inductor Layout With Dummy Structures for BPR Porting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current design rules for semiconductor devices are specific to a particular technology node and do not facilitate seamless adaptation between non-buried power rail (non-BPR) and buried power rail (BPR) architectures, requiring new patterns or extensions in layout diagrams, which complicates the porting of circuit designs across different architectures.
Innovation Solution
A dual-architecture-compatible layout diagram is generated, allowing patterns to be selectively pruned to yield either a non-BPR or BPR type of architecture without adding new patterns or extending existing ones, by including dummy structures that are artifacts of the dual-architecture design, facilitating adaptation into either architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If design rules are specific to a particular technology node, then manufacturing precision for that node is improved, but adaptability to different architectures (non-BPR and BPR) deteriorates
Solution Approach 1:
The patent creates a universal layout diagram that can serve multiple architecture types (both non-BPR and BPR) through the same design rules. By incorporating dummy structures that are selectively retained or removed based on the target architecture, a single layout diagram achieves multi-functionality, eliminating the need for separate design rule sets for different architectures while maintaining manufacturing precision for each specific node.
Solution Approach 2:
The patent applies preliminary action by pre-including dummy structures in the layout diagram during the design phase. These dummy structures are placeholders that anticipate future architecture-specific modifications. By preparing the layout with these pre-placed dummy elements, the design can be easily adapted to different architectures without requiring fundamental redesign, thus resolving the contradiction between precision and adaptability.
2Adaptability or versatility
If new patterns or extensions are added to layout diagrams for architecture adaptation, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent applies the extraction principle by removing dummy structures from the layout diagram when adapting to a specific architecture. Instead of maintaining complex multi-architecture support in the final design, the unnecessary dummy elements are extracted or pruned away, leaving a simplified layout that is optimized for the target architecture. This reduces device complexity while preserving adaptability during the design phase.
Solution Approach 2:
The patent implements discarding and recovering by temporarily including dummy structures during the design phase (recovering flexibility) and then discarding them when the final architecture-specific layout is generated. This allows the design process to benefit from enhanced adaptability without the final device bearing the complexity burden of retained dummy elements.
3Adaptability or versatility
If dummy structures are included in layout diagrams, then adaptability between architectures is improved, but manufacturing precision may deteriorate due to additional artifact structures
Solution Approach 1:
The patent applies parameter changes by modifying the presence or absence of dummy structures based on the target architecture type. For non-BPR architectures, certain dummy structures are retained, while for BPR architectures, different dummy structures are retained or removed. This parameter-based control allows the manufacturing process to be optimized for each architecture type, maintaining manufacturing precision while achieving adaptability through selective inclusion or exclusion of dummy elements.
Data Source
AI summary
A semiconductor device includes in a transistor layer, components of corresponding transistors (transistor components); in corresponding layers below the transistor layer (sub-TR layers), various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and which are included because the semiconductor device has a buried power rail (BPR) architecture; and in corresponding layers over the transistor layer (supra-TR layers), various dummy structures (dummy supra-TR structures) which are included as artifacts resulting from the semiconductor device being based on a dual-architecture-compatible design which is substantially equally suitable either to adaptation into a non-BPR architecture or adaptation into the BPR architecture; and the semiconductor device being an inductor.