Multilayer Inductor Go-Around Wiring Reduces Parasitic Capacitance
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Solution Overview
Problem
Inductors constructed in a planar manner face challenges in increasing the number of turns without enlarging the device size, leading to high parasitic capacitance and reduced usable frequency due to small interlayer film thickness in multilayer wiring layers on semiconductor substrates.
Innovation Solution
An inductor design with go-around wiring formed in multiple adjacent wiring layers, where one end of each go-around wiring is connected via a via, allowing the go-around wiring to be placed at the same position on the substrate, reducing parasitic capacitance between upper and lower layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of turns is increased to increase inductance in planar inductors, then inductance is improved, but device size increases
Solution Approach 1:
The patent transitions from planar two-dimensional winding to three-dimensional multilayer winding structure. Conductors are arranged in multiple stacked layers with vertical spacing, enabling the inductor to utilize the third dimension (height) for additional turns without increasing the planar footprint. This dimensional transition allows significant inductance increase while maintaining compact device area.
2Reliability
If multilayer wiring layers are used to increase turns, then inductance is improved, but parasitic capacitance increases due to small interlayer film thickness
Solution Approach 1:
The patent introduces a resin layer as an intermediary dielectric material between adjacent conductors in different layers. This resin layer provides electrical insulation and controls the parasitic capacitance between layers. By selecting appropriate resin material properties and thickness, the design achieves balanced electrical performance with reduced harmful capacitive coupling while maintaining the multilayer structure benefits.
Solution Approach 2:
The patent optimizes physical parameters including conductor spacing, layer thickness, and dielectric material properties to control parasitic capacitance. By adjusting these parameters, the design achieves reduced interlayer capacitance while maintaining sufficient turns for required inductance values.
3Ease of manufacture
If planar inductor structure is used, then manufacturing is simplified, but the number of turns is limited without increasing device size
Solution Approach 1:
The patent extends the winding structure into the vertical dimension with multiple stacked layers, allowing significantly more turns to be packed into the same planar area. This three-dimensional arrangement maintains compatibility with standard semiconductor manufacturing processes while achieving higher turn counts and inductance values that would be impossible with planar structures alone.
Data Source
AI summary
Parasitic capacitance between upper and lower adjacent wirings of an inductor using a multilayer wiring layer in an insulating film formed on a base substrate is reduced. An inductor is characterized by having one go-around of go-around wiring (A-B or B-C) formed in each of at least two of adjacent wiring layers of a plurality of wiring layers 18 placed in an insulating film on a base substrate, and in that one end (B) of the one go-around of go-around wiring (A-B and B-C) formed in each of the at least two of wiring layers is connected to each other at a via and the one go-around of go-around wiring (A-B and B-C) formed in each of the at least two of wiring layers is placed at substantially the same position in a surface of the base substrate when viewed from an upper side of the base substrate.