Inductor Groove Insulation for Semiconductor Signal Transfer

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Solution Overview

Problem

The miniaturization of photocouplers is hindered by the presence of light emitting and receiving elements, and they struggle with high-frequency signal transmission due to the difficulty in achieving precise alignment and isolation between inductors in semiconductor devices.

Innovation Solution

Forming a groove between the first and second inductors on the same substrate to enhance insulation and alignment, allowing for improved signal transfer efficiency and preventing electrical connection issues caused by metal migration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If inductors are placed close together for miniaturization, then device size is reduced, but isolation between inductors deteriorates due to metal migration

Engineering Contradiction:
Improvedevice sizeVSAvoidisolation between inductors
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The groove structure segments the substrate between closely spaced inductors, providing physical separation that prevents metal migration while allowing the inductors to remain close for miniaturization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating grooves only in specific regions between inductors where metal migration is a concern, rather than uniformly across the entire substrate. This allows close spacing in some areas while maintaining isolation where needed.

Inventive Principle:
Principle #3Local quality

2Reliability

If a thick isolation layer is added between inductors to prevent metal migration, then isolation is improved, but manufacturing complexity increases and standard CMOS process cannot be used

Engineering Contradiction:
Improveisolation between inductorsVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

Instead of adding thickness in the vertical dimension (thick isolation layer), the patent uses grooves that extend in the horizontal dimension between inductors. This dimensional approach maintains isolation functionality while staying compatible with standard planar CMOS manufacturing processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent extracts the isolation function from the vertical stacking approach (thick layers) and implements it through lateral groove structures, simplifying the manufacturing process to standard CMOS compatibility.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration ensures high signal transfer efficiency and maintains insulation between inductors, reducing manufacturing costs and improving the reliability of semiconductor devices by ensuring precise alignment and preventing electrical contact issues.

Implementation Method 1

a technique of transferring an electric signal by arranging two (one set of) inductors to face each other and inductively coupling the respective inductors to each other

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS10249565B2Semiconductor device that transfers an electric signal with a set of inductors
Publication Date: 2019.04.02 RENESAS ELECTRONICS CORP
  • US10249565B2 patent drawing
  • US10249565B2 patent drawing
  • US10249565B2 patent drawing

AI summary

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.