Integrated Inductor Metal Patterned Ground Shield Eddy Current Blocking

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Solution Overview

Problem

Integrated inductors on silicon substrates suffer from low Q-factor due to substrate loss and inefficiencies in blocking deep eddy currents, particularly with polysilicon patterned ground shields (PGS) providing inadequate blocking effects.

Innovation Solution

The integration of a semiconductor substrate with a specific patterned ground shield (PGS) formed by deep trenches or through silicon vias (TSVs) filled with metal materials like copper or gold, which are arranged to block eddy currents effectively and increase the Q-factor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a polysilicon patterned ground shield (PGS) is formed between the inductor and gate oxide layer, then the eddy current blocking effect is provided, but the deep eddy current in the semiconductor substrate cannot be effectively blocked and the Q-factor is insufficient

Engineering Contradiction:
ImproveQ-factorVSAvoideddy current loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent changes the material parameter from polysilicon to metal (such as copper or aluminum) for the patterned ground shield. This material substitution significantly improves the eddy current blocking capability, particularly for deep eddy currents in the semiconductor substrate, thereby increasing the Q-factor and reducing energy loss.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extends the PGS structure into the substrate depth dimension by forming metal-filled trenches or via holes that penetrate through the substrate. This three-dimensional configuration provides effective blocking for deep eddy currents that cannot be addressed by traditional planar PGS structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of energy

If traditional polysilicon PGS is used, then the structure is simple to fabricate, but the eddy current blocking efficiency is insufficient

Engineering Contradiction:
Improveeddy current blocking efficiencyVSAvoidfabrication complexity
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The patent changes the material parameter from polysilicon to metal (such as copper or aluminum) for the patterned ground shield. This material substitution significantly improves the eddy current blocking capability, particularly for deep eddy currents in the semiconductor substrate, thereby increasing the Q-factor and reducing energy loss.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent combines the PGS function with existing metal interconnect layers or substrate structures. By integrating the metal PGS with the substrate fabrication process and existing metal layers, the additional manufacturing steps are minimized while achieving improved eddy current blocking.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively blocks deep eddy currents and enhances the Q-factor of integrated inductors, improving their performance by replacing traditional polysilicon PGS with more efficient metal-based PGS, applicable in various IC configurations including 3D ICs and Flip Chips.

Implementation Method 1

the integrated inductor has low Q-factor problem due to substrate loss. Thus, a patterned ground shield (PGS) formed by polysilicon is utilized for reducing eddy current of the integrated inductor to increase Q-factor.

Methodology Applied
Scientific EffectEddy current: Eddy Currents

Data Source

PatentUS9214511B2Integrated inductor and integrated inductor fabricating method
Publication Date: 2015.12.15 REALTEK SEMICON CORP
  • US9214511B2 patent drawing
  • US9214511B2 patent drawing
  • US9214511B2 patent drawing

AI summary

The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS).