Inductor Stack Structure With Thick Through-Holes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits face challenges with low-quality inductors and large inductor areas, which affect circuit performance and integration, making it difficult to achieve high inductance values and quality factors while minimizing circuit size and manufacturing costs.
Innovation Solution
The inductor stack structure includes multiple metal layers with first plane inductors connected through a through hole thicker than the metal layers, reducing parasitic capacitance and increasing mutual inductance, allowing for high inductance values and quality factors while minimizing the inductor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple metal layers with plane inductors are stacked to increase inductance value, then inductance value increases, but parasitic capacitance between layers increases and quality factor decreases
Solution Approach 1:
The patent transitions from planar inductor design to three-dimensional stacked inductor design. Multiple metal layers are stacked vertically with through-holes connecting corresponding inductors in adjacent layers in series. This vertical stacking approach increases inductance value by utilizing the third dimension while maintaining compact footprint area, effectively resolving the contradiction between achieving high inductance and minimizing area.
2Area of stationary object
If inductor area is reduced for better integration, then circuit size decreases, but inductance value and quality factor become difficult to maintain
Solution Approach 1:
The patent employs vertical stacking of multiple metal layers to achieve high inductance values within a reduced footprint area. By connecting inductors in series through vertically aligned through-holes, the design accumulates inductance along the vertical dimension rather than expanding horizontally, thus maintaining small inductor area while achieving required inductance values for better circuit integration.
3Area of stationary object
If inductor area is reduced for better integration, then circuit size decreases, but quality factor becomes difficult to maintain
Solution Approach 1:
The stacked inductor configuration achieves high quality factor by utilizing vertical stacking with series-connected through-holes. This approach maintains low parasitic capacitance compared to parallel connections, preserving quality factor while reducing footprint area for better circuit integration.
4Reliability
If through hole thickness is increased to reduce parasitic capacitance, then parasitic capacitance decreases and quality factor improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the inductor structure into multiple discrete metal layers separated by insulating layers, with through-holes providing vertical connections. Each layer can be independently patterned and connected, allowing precise control of parasitic capacitance through through-hole dimensional optimization while maintaining manufacturability through standardized multi-layer PCB fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains high inductance values and quality factors while reducing the integrated circuit area, effectively addressing the limitations of existing inductor designs by enhancing inductance and quality factor performance without increasing the inductor area.
Implementation Method 1
the parasitic capacitance between different metal layers may be greatly reduced
Implementation Method 2
each of the at least two metal layers at least comprises a first plane inductor
Data Source
AI summary
Provided is an inductor stack structure. The inductor stack structure include a substrate; at least two metal layers sequentially stacked on one side of the substrate, each metal layer at least comprises a first plane inductor; a through hole, which is located between any two neighboring metal layers, first plane inductors in different metal layers are electrically connected through the through hole; and a thickness of the through hole is greater than that of the metal layer.