Inductorless LNA With Current Reuse for Programmable RF Delay
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Solution Overview
Problem
Current RF delay devices are unable to achieve sufficient delays (>100 ns) required for full-duplex RF wireless systems and other applications due to limitations in area efficiency and power consumption, with existing solutions either being non-programmable or having narrow bandwidths.
Innovation Solution
A low noise amplifier (LNA) design utilizing an inductorless chip architecture with current reuse, bias sharing, and limited AC coupling capacitors, combined with a time-interleaved multistage switched-capacitor architecture, to achieve programmable delays while reducing power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If acoustic delay lines are used to achieve >100 ns of RF delay, then delay requirement is met, but bandwidth is narrow and area is large
Solution Approach 1:
The patent replaces acoustic delay lines (mechanical wave propagation) with electronic delay circuits (voltage signal propagation through switched-capacitor networks and buffers). This substitution enables programmable delay values and broader bandwidth operation while reducing the physical area required, as electronic signals propagate much faster than acoustic waves in the same medium.
Solution Approach 2:
The patent implements programmable delay values through digital control of switched-capacitor networks, allowing the delay to be dynamically adjusted between different preset values (e.g., 0, 16, 32, 48 ns in 4 ns steps). This dynamic programmability replaces the fixed delay characteristic of acoustic lines, enabling adaptation to different application requirements without changing the physical hardware configuration.
2Power
If conventional LNA designs are used, then amplification is achieved, but power consumption is high and area is large
Solution Approach 1:
The patent combines the LNA functionality with the delay circuitry into a single integrated structure. The low-noise amplifier stage is directly coupled with the switched-capacitor delay networks, sharing common biasing circuits and transistor structures. This merging eliminates the need for separate LNA and delay blocks, reducing total power consumption and chip area while maintaining both amplification and delay functions.
Solution Approach 2:
The patent designs the LNA to serve multiple functions: it provides signal amplification, impedance matching, and acts as part of the delay path for the RF signal. The same transistors and biasing networks are used for both amplification and delay control, making the circuit universal in its functionality and reducing the overall component count, power consumption, and area.
3Duration of action of moving object
If RF delay devices with sufficient delay (>100 ns) are implemented, then full-duplex cancellation is enabled, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the total delay requirement into multiple smaller delay stages that can be programmably combined. Instead of using a single large delay block, the circuit divides the delay into discrete steps (e.g., multiple 16 ns stages that can be selectively enabled). This segmentation reduces the complexity of each individual stage, allows for easier programmability, and simplifies the control logic while achieving the total required delay of >100 ns.
Data Source
AI summary
A low noise amplifier (LNA) offering one or more of the following benefits: increased gain, reduced power consumption, and/or reduced area, while achieving a similar noise figure, is disclosed. The LNA achieves these benefits by employing an inductorless chip design, current reuse among the transistors, bias sharing, limited AC coupling capacitors, common gate input device feedback, and careful sizing of the transistors.