Inference Task Scheduling Across SIMD and SIMT Execution Phases
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Solution Overview
Problem
Existing graphics processing technologies face challenges in efficiently handling resource-intensive tasks such as ray tracing and rasterization, particularly in real-time applications, due to the computational demands of operations like ray-scene intersection and rasterization.
Innovation Solution
The implementation of a hybrid graphics processing architecture that incorporates dedicated sets of graphics processing resources, including tensor cores and ray tracing cores, optimized for parallel processing of graphics and compute operations, along with a scheduling mechanism to manage workload distribution across these cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ray tracing is used to simulate light transport through physically-based rendering, then rendering quality is improved, but computational resource consumption increases
Solution Approach 1:
The patent segments the graphics processing workload by introducing dedicated ray tracing cores separate from traditional rasterization units. These specialized cores handle ray-scene intersection computations independently, allowing the system to perform ray tracing operations without overloading the general-purpose graphics processing units, thus maintaining rendering quality while managing computational resources more efficiently.
Solution Approach 2:
The patent implements local quality by creating specialized hardware units with specific functions - ray tracing cores for ray-scene intersections, rasterization units for triangle-to-pixel conversion, and tensor cores for machine learning operations. Each unit is optimized for its specific task, allowing the system to achieve high rendering quality in ray tracing operations while consuming computational resources only where needed rather than using a monolithic processing approach.
2Speed
If ray tracing operations are performed in real-time applications, then real-time performance is achieved, but computational demands increase
Solution Approach 1:
The patent applies preliminary action by pre-building bounding volume hierarchies (BVH) for scene geometry before ray tracing operations begin. This preprocessing organizes the scene data into an optimized structure that enables faster ray-scene intersection tests during real-time rendering. By preparing the scene data in advance, the system reduces the computational burden during actual ray tracing execution, making real-time performance achievable.
Solution Approach 2:
The patent extracts the computationally intensive ray-scene intersection tests from the general graphics processing pipeline and places them in dedicated ray tracing cores. This separation removes the bottleneck from the main rendering pipeline, allowing real-time performance by handling the most demanding computations in specialized units that can operate independently and in parallel.
3Productivity
If dedicated graphics processing resources are added for ray tracing and tensor operations, then processing capability is improved, but device complexity increases
Solution Approach 1:
The patent implements universality by designing a unified graphics processing architecture where multiple core types (ray tracing cores, rasterization units, tensor cores) coexist and can be scheduled dynamically based on workload requirements. The scheduler manages these diverse resources, allowing them to handle different types of operations efficiently. This multi-functional approach increases processing capability while managing complexity through a single integrated system rather than separate independent units.
Solution Approach 2:
The patent applies dynamics through its scheduling mechanism that can dynamically allocate and switch between different types of processing cores based on the current workload. The scheduler can adaptively determine whether to use ray tracing cores for ray-scene intersections, rasterization units for traditional graphics, or tensor cores for machine learning operations. This dynamic resource allocation optimizes processing capability for varying workloads while managing device complexity through flexible, adaptive control.
Data Source
AI summary
Apparatus and method for scheduling inference tasks. For example, one embodiment of an apparatus comprises: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.