FinFET Channel with III-V Bi-layers for Low Trap Density
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Solution Overview
Problem
III-V semiconductor materials used in semiconductor devices have conduction band and valence band energies that are ill-suited for mass production and exhibit high trap density at the interface with gate dielectrics, limiting their effectiveness in consumer devices.
Innovation Solution
A FinFET transistor structure is developed with a channel region formed by alternating layers of III-V materials like indium arsenide and gallium antimonide, where the properties of each layer are modulated to achieve a desired band gap and reduced interface trap density, using epitaxial growth processes to control layer thickness and composition for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-V materials are used as semiconductor materials, then band gap functionality is achieved, but interface trap density becomes exceedingly high
Solution Approach 1:
A first barrier layer is introduced as an intermediary between the III-V semiconductor material and the gate dielectric. This barrier layer has a conduction band offset with the III-V material that is less than the conduction band offset of the gate dielectric, creating a transition region that reduces interface trap density while preserving the functional band gap properties of the III-V material.
Solution Approach 2:
The semiconductor structure is formed as a composite system comprising the III-V material layer combined with the first barrier layer and gate dielectric layer. This composite structure leverages the advantageous band gap properties of III-V materials while mitigating their high interface trap density through the carefully engineered barrier layer with specific conduction band offset characteristics.
2Reliability
If III-V materials are used, then semiconductor functionality is achieved, but conduction band and valence band energies are ill-suited for mass production
Solution Approach 1:
The conduction band offset parameter is specifically engineered by selecting a first barrier layer material whose conduction band offset with the III-V material is less than the conduction band offset of the gate dielectric. This parameter adjustment optimizes the band alignment for mass production compatibility while maintaining semiconductor functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modulated channel region achieves a small band gap with low interface trap density, improving switching behavior and reducing degradation of drive and off-state currents, leading to more ideal device operation.
Implementation Method 1
The channel region includes a first layer on the substrate, the first layer including a first III-V material, and a second layer on the first layer, the second layer including a second III-V material different from the first III-V material
Data Source
AI summary
A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.