InFO Package Dielectric Layer Height Variation Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging of semiconductor devices due to the need for smaller, more creative packaging techniques that can accommodate increasing integration density, higher speed, and lower power consumption, which existing methods struggle to address effectively.
Innovation Solution
The development of an Integrated Fan-Out (InFO) package structure that includes dies and through vias with redistribution lines, where a series of photolithography processes are used to form a dielectric layer with reduced height variations, allowing for more flexible and cost-effective packaging by eliminating the need for grinding and chemical mechanical polishing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional packaging methods are used, then manufacturing process is simpler, but height variations in dielectric layer require additional grinding and chemical mechanical polishing steps
Solution Approach 1:
The patent applies preliminary action by performing multiple photolithography exposures at different exposure doses before the dielectric layer is fully formed. This preliminary patterning at different exposure doses creates a pre-formed structure that inherently compensates for height variations, eliminating the need for subsequent grinding and chemical mechanical polishing steps to achieve the desired planarity.
2Volume of moving object
If miniaturization is pursued to reduce device size, then integration density increases, but packaging becomes more difficult
Solution Approach 1:
The patent applies dimensionality change by transitioning from traditional planar packaging to three-dimensional stacked packaging with through vias extending vertically through multiple dielectric layers. This vertical dimensionality allows for higher integration density and miniaturization while maintaining manufacturability, as the through vias provide direct electrical connections between stacked dies without requiring complex lateral routing.
3Reliability
If through vias are added for redistribution, then electrical connections are improved, but manufacturing process becomes more complex
Solution Approach 1:
The patent applies merging by combining the formation of through vias with the dielectric layer deposition and photolithography processes. The through vias are formed by patterning the dielectric layer itself using photolithography, rather than as a separate mechanical drilling operation. This merging of processes improves electrical connections while avoiding the addition of complex separate manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a more efficient and cost-effective packaging solution by reducing height variations in the dielectric layer, allowing for improved electrical connections and flexibility in through via placement, thereby addressing the need for smaller and more complex semiconductor device packaging.
Implementation Method 1
a series of photolithography processes are used to form a dielectric layer with reduced height variations
Data Source
AI summary
A package structure and method of making the same is provided. A through via is formed on a substrate, the through via extending through a molding material. An upper surface of the molding material is recessed from an upper surface of the through via. A dielectric layer is deposited over the through via and the molding material. The dielectric layer has a first upper surface with a first variation in height between a first area disposed over the through via and a second area disposed over the molding material. Exposure processes are performed on the dielectric layer. The dielectric layer is developed. After the developing, the dielectric layer has a second upper surface with a second variation in height between the first area and the second area. The first variation is greater than the second variation.