InFO Package Dielectric Stack for Large High-Bandwidth Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in reducing the physical size of semiconductor devices while maintaining performance and reliability, particularly in achieving high bandwidth and thermal management for large package applications.
Innovation Solution
The integration of an integrated fan out (InFO) process with an Ajinomoto build up film (ABF) or prepreg lamination process, along with the use of a composite redistribution layer and polyimide top dielectric layers, enables the creation of smaller and more efficient semiconductor devices with improved electrical performance and thermal expansion matching that of printed circuit boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor process node is reduced to sub-20 nm to increase integration density, then more components can be integrated into a given area, but manufacturing complexity and difficulty increase significantly
Solution Approach 1:
The patent transitions from planar 2D integration to 3D stacked architecture, where multiple semiconductor dies are vertically bonded together. This dimensional change allows continued scaling and increased functionality without further reducing the lateral feature size, thereby avoiding the manufacturing complexity associated with sub-20 nm processes while maintaining high integration density.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate dies that are fabricated independently and then bonded together in a stacked configuration. Each die can be optimized and manufactured separately using mature process nodes, avoiding the need for all components to be manufactured at difficult sub-20 nm nodes, thus reducing overall manufacturing complexity.
2Volume of moving object
If stacked and bonded semiconductor devices are used to reduce physical size, then device footprint is reduced, but bonding process complexity increases
Solution Approach 1:
The patent employs a carrier substrate that serves multiple functions: it provides mechanical support during handling, enables precise alignment of multiple dies through alignment marks, facilitates bonding through controlled temperature and pressure, and allows for subsequent release of the completed stacked device. This multi-functional carrier reduces the need for separate specialized equipment for each bonding step, simplifying the overall process.
Solution Approach 2:
The patent pre-forms alignment marks and bonding interfaces on the carrier substrate before die attachment. The carrier is prepared with specific structural features that guide die placement and ensure proper alignment, eliminating the need for complex real-time alignment procedures during bonding, thus reducing bonding process complexity.
3Reliability
If larger package sizes are used for high bandwidth applications, then electrical performance improves, but board-level reliability stresses and manufacturing difficulty increase
Solution Approach 1:
The patent achieves high bandwidth electrical performance by stacking dies vertically with short inter-die connection paths, effectively creating high-speed connections in the vertical dimension rather than requiring large lateral trace lengths. This reduces the package footprint while maintaining low signal propagation delay and high bandwidth, avoiding the manufacturing difficulties associated with large package handling and assembly.
Data Source
AI summary
An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.