InFO Alignment Mark Layout for Dense I/O Redistribution
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Solution Overview
Problem
The increasing miniaturization of semiconductor dies and the need for higher I/O pad density in packaging pose challenges, including limited pad numbers due to pitch constraints and the risk of solder bridges, which complicates packaging and reduces yield.
Innovation Solution
The development of an Integrated Fan-Out (InFO) package with alignment marks featuring grating patterns, allowing for the redistribution of I/O pads to a larger area and improved alignment accuracy through elongated and narrower strips, facilitating higher pad density without delamination issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of I/O pads is decreased to increase pad density, then the number of I/O pads that can be packed increases, but solder bridges may occur reducing packaging yield
Solution Approach 1:
The patent transitions from traditional fan-in packaging where I/O pads are confined to the die surface to fan-out packaging where the package substrate area exceeds the die area. This dimensional expansion allows I/O pads to be redistributed over a larger area, increasing pad density while maintaining adequate spacing to prevent solder bridges, thus resolving the contradiction between pad quantity and packaging reliability
2Productivity
If dies are packaged before sawing to increase throughput and reduce cost, then productivity improves, but the limited die area restricts the number of I/O pads that can be accommodated
Solution Approach 1:
By implementing fan-out packaging where the package substrate is larger than the die, the patent enables wafer-level packaging to accommodate more I/O pads. The expanded area allows redistribution of pads beyond the original die boundaries, resolving the limitation of pad quantity while preserving the productivity benefits of pre-saw packaging
Solution Approach 2:
The patent separates the die from its original substrate and redistributes the I/O pads onto a larger package substrate. This segmentation allows the die to be packaged at wafer level with expanded I/O capacity, maintaining high throughput while increasing the number of accommodated pads
3Ease of manufacture
If alignment marks with traditional patterns are used, then manufacturing is simpler, but alignment accuracy deteriorates with multiple dielectric layers reducing clarity
Solution Approach 1:
The patent applies different structural characteristics to different parts of the alignment mark. The elongated and narrowed strip design creates distinct local features that maintain high contrast and visibility through multiple dielectric layers, improving alignment accuracy while remaining compatible with standard manufacturing processes
Data Source
AI summary
A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.