InFO Redistribution Structure With Planarized Seal Ring Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving compact and efficient packaging for smaller electronic components due to the need for increased integration density, which requires innovative manufacturing processes for integrated fan-out (InFO) packages.
Innovation Solution
The manufacturing process for InFO packages involves forming a redistribution structure on a carrier with a de-bonding layer, followed by the integration of dies and encapsulation. This process includes the formation of conductive structures, seed material layers, and dielectric layers, with specific planarization and recessing techniques to achieve optimal topography and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum feature size is reduced to increase integration density, then more electronic components can be integrated into a given area, but the packaging becomes more challenging and requires compact designs
Solution Approach 1:
The patent transitions from traditional two-dimensional packaging layouts to three-dimensional stacked architectures, allowing electronic components to be arranged vertically across multiple layers. This dimensional change enables higher integration density without proportionally increasing the horizontal package footprint, thereby managing packaging complexity while achieving greater component integration.
Solution Approach 2:
The patent implements nested structures where smaller components and interconnect structures are embedded within larger package architectures. Multiple functional layers are nested vertically, with each layer containing conductive structures, dielectric materials, and electronic components that are integrated within the overall package volume, enabling compact high-density integration.
2Reliability
If multiple layers of conductive structures and dielectric layers are formed to achieve electrical connectivity, then electrical connections can be established between multiple components, but the manufacturing process becomes more complex
Solution Approach 1:
The patent employs preliminary formation of conductive structures and dielectric layers in a systematic sequence before final component assembly. Seed material layers are deposited first, followed by controlled formation of conductive patterns and dielectric structures in predetermined positions. This preliminary structuring establishes the electrical connectivity framework in advance, simplifying subsequent assembly steps and reducing overall manufacturing complexity.
Solution Approach 2:
The manufacturing process is segmented into distinct fabrication stages: seed layer deposition, conductive structure formation, dielectric layer deposition, and planarization. Each stage focuses on forming specific structural elements independently, allowing for controlled process optimization and simplified quality management while achieving complex multi-layer electrical connectivity.
3Manufacturing precision
If planarization and recessing techniques are applied to achieve optimal topography, then the surface flatness and component alignment are improved, but additional manufacturing steps are required
Solution Approach 1:
The patent introduces dielectric layers as intermediary materials between conductive structures and subsequent components. These dielectric layers serve as mediators that provide planarization and surface flatness control, enabling precise component alignment while integrating the topography control function into the existing layer formation process rather than requiring separate dedicated planarization steps.
Solution Approach 2:
The patent combines multiple functions into unified manufacturing steps: dielectric layer deposition simultaneously provides electrical insulation, surface planarization, and mechanical support; recessing operations are integrated with subsequent material deposition steps. This merging of functions reduces the number of discrete manufacturing steps while maintaining the required surface precision for component alignment.
Data Source
AI summary
A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.