InFO Redistribution Structure With Seal Ring for Dense Packaging

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Solution Overview

Problem

The semiconductor industry faces challenges in creating compact electronic packages with high integration density due to the need for smaller feature sizes, which requires innovative manufacturing processes for integrated fan-out (InFO) packages that can efficiently integrate and connect electronic components while maintaining reliability and accuracy.

Innovation Solution

The manufacturing process involves a carrier with a de-bonding layer, a redistribution structure with conductive and dielectric layers, and a series of deposition and etching steps to form conductive structures, encapsulate dies, and create seal ring elements and vias, allowing for precise electrical connections and encapsulation, enabling the formation of reliable InFO packages with high integration density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If feature size is reduced to increase integration density, then more electronic components can be integrated into a given area, but manufacturing precision and reliability become more difficult to maintain

Engineering Contradiction:

Improveintegration densityVSAvoidfeature size precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent divides the semiconductor structure into multiple functional layers including dielectric layers, conductive layers, and seal ring elements. Each layer is formed through separate deposition and etching steps, allowing independent optimization of each layer's dimensions and properties, which maintains manufacturing precision while achieving high integration density through vertical stacking

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar integration to three-dimensional vertical integration by stacking multiple functional layers (dielectric layers 530, 532, conductive layers, seal ring elements) in the vertical dimension. This allows integration density to increase through vertical space utilization rather than horizontal scaling, thereby maintaining manufacturing precision requirements

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If compact package design is implemented to reduce package size, then smaller electronic components are achieved, but electrical connectivity and reliability may be compromised

Engineering Contradiction:

Improvepackage sizeVSAvoidelectrical connectivity

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent implements a nested structure where seal ring elements are positioned within recesses of dielectric layers, and conductive layers are embedded within dielectric layers. This nested arrangement maximizes space utilization within the compact package volume while maintaining proper electrical isolation and connectivity pathways, ensuring reliability despite reduced package size

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent introduces dielectric layers as intermediary materials between conductive elements and seal ring structures. These dielectric layers provide electrical isolation and mechanical support, ensuring reliable electrical connectivity while enabling the compact vertical stacking arrangement that reduces overall package volume

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This process enables the creation of compact InFO packages with enhanced electrical connectivity and reliability, supporting the integration of high-density electronic components and facilitating the formation of accurate and efficient redistribution structures within the semiconductor industry.

Implementation Method 1

the de-bonding layer DB allows the structure subsequently formed on the carrier C in the following processes to be separated from the carrier C

Methodology Applied

Scientific EffectLight-to-heat conversion:

Implementation Method 2

a plasma process is performed to the first dielectric layer 530 to form the recessed first dielectric layer 530r

Methodology Applied

Scientific EffectPlasma: Plasma

Implementation Method 3

a first conductive pattern 540a and a first seal ring element 540b are respectively formed on the first conductive via 520a and the first conductive via 520b

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11798893B2Semiconductor package and manufacturing method thereof

Publication Date: 2023.10.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.