InFO Redistribution Structure With Seal Ring for Precise Via Topography
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving compact and efficient packaging for smaller electronic components due to the continuous reduction in minimum feature size, which requires innovative manufacturing processes for integrated fan-out (InFO) packages.
Innovation Solution
The manufacturing process for InFO packages involves forming a redistribution structure on a carrier with a de-bonding layer, attaching conductive structures and dies, encapsulating them, and then forming conductive vias and seal ring elements through various deposition and etching processes, followed by planarization and recessing of dielectric layers to achieve precise topography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more electronic components can be integrated into a given area, but manufacturing precision and packaging complexity increase
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical stacking with multiple die layers (first die, second die, third die) connected through conductive vias and interconnect structures. This dimensional change allows integration density to increase vertically rather than being constrained by horizontal feature size reduction, thereby maintaining manufacturability while achieving higher component density.
Solution Approach 2:
The patent implements nested packaging where multiple dies are stacked vertically within a single package footprint, with smaller feature-sized conductive vias nested within the larger die structures. The conductive vias are nested within dielectric layers, and multiple die layers are nested within the same package boundary, effectively increasing integration density without proportionally reducing minimum feature size.
2Volume of moving object
If compact packaging is implemented for smaller components, then package size is reduced, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct modular stages: carrier preparation with de-bonding layer, first die attachment with redistribution structure, second die stacking, conductive via formation, encapsulation, and final planarization. Each stage can be independently optimized and controlled, managing overall process complexity while achieving compact packaging.
Solution Approach 2:
The de-bonding layer is pre-formed on the carrier substrate before die attachment, enabling subsequent easy separation of the finished package from the carrier. The redistribution structure is pre-configured on the first die before stacking, ensuring proper electrical interconnection without requiring complex post-assembly routing. These preliminary actions simplify the overall manufacturing process despite the compact multi-layer structure.
3Manufacturing precision
If multiple deposition and etching processes are used to form conductive vias and seal ring elements, then manufacturing precision is improved, but production time increases
Solution Approach 1:
The patent combines multiple deposition steps (seed layer deposition, conductive material deposition) and etching steps (via etching, seal ring etching) into integrated process sequences. The conductive via formation merges seed layer deposition, pattern definition, and material filling in a coordinated sequence. The seal ring element formation combines deposition and etching in a single process flow, achieving high precision while minimizing the cumulative time of separate operations.
Solution Approach 2:
The manufacturing process maintains continuous useful action by performing deposition and etching operations in an uninterrupted sequence without unnecessary intermediate steps. The conductive via formation continues directly from seed layer deposition through pattern definition to material filling. The seal ring elements are formed in continuous operation immediately following via formation, eliminating idle time while maintaining precision through consistent process parameters throughout the continuous operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the creation of InFO packages with improved topography and reliability, allowing for accurate formation of subsequent elements and enhanced integration density, thus addressing the need for compact packaging in the semiconductor industry.
Implementation Method 1
the de-bonding layer DB allows the structure subsequently formed on the carrier C in the following processes to be separated from the carrier C
Implementation Method 2
The plasma process is then performed to the first dielectric layer 530 to form the recessed first dielectric layer 530r
Implementation Method 3
various deposition and etching processes
Data Source
AI summary
A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.