InFO Package Substrate Layout for Low-Warpage Interconnect
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Solution Overview
Problem
The increasing complexity and size of integrated circuits lead to warpage issues and reduced manufacturing yield due to the embedding of Local Silicon Interconnect (LSI) dies in traditional Chip-on-Wafer-on-Substrate packages, which complicates the packaging process and increases insertion loss.
Innovation Solution
The development of an Integrated Fan-Out (InFO) package substrate with an embedded LSI die, allowing for direct bonding of discrete device dies and package components, reducing warpage and improving yield by extending the package substrate laterally beyond the dies and bonding it with an organic package substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Local Silicon Interconnect (LSI) dies are embedded in traditional Chip-on-Wafer-on-Substrate packages, then electrical interconnectivity is improved, but warpage increases and manufacturing yield decreases
Solution Approach 1:
The patent transitions from a vertical stacking architecture (Chip-on-Wafer-on-Substrate) to a lateral integration architecture (Integrated Fan-Out). The LSI die is embedded within the organic package substrate itself, and device dies are bonded laterally to the substrate in the same plane. This dimensional reconfiguration reduces cumulative warpage while maintaining electrical interconnectivity through the substrate's redistribution layers and conductive vias.
Solution Approach 2:
The patent merges the LSI die embedding function directly into the organic package substrate structure. Rather than embedding LSI dies in separate wafer layers as in traditional CoWoS, the LSI die is integrated within the substrate's internal layers, combining the substrate's structural support function with the LSI's interconnect function in a single unified component.
2Adaptability or versatility
If package size and complexity are increased to integrate more functions, then functionality is improved, but warpage increases
Solution Approach 1:
The patent segments the package into distinct functional modules: the organic package substrate with embedded LSI die serves as the interconnect backbone, while multiple device dies (CPU, GPU, memory, etc.) are bonded as separate functional units to the substrate. This modular segmentation allows each component to be optimized independently and reduces cumulative warpage compared to monolithic multi-layer stacking.
Solution Approach 2:
The patent implements local quality by providing different structural characteristics in different regions of the package substrate. The substrate includes varying thickness regions, localized reinforcement structures, and region-specific redistribution layer configurations that optimize each area for its specific function while collectively managing warpage across the entire large-scale package.
Data Source
AI summary
A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.