InFO Through-Via Packaging Without Laser Drilling
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Solution Overview
Problem
The increasing miniaturization of semiconductor chips and the need for more integrated functions lead to higher I/O pad density, making packaging more complex and costly, posing a challenge in reducing production complexity and cost.
Innovation Solution
An Integrated Fan-Out (InFO) package is developed without a laser drill process, using a sacrificial layer to replace the existing dielectric layer, which allows for the formation of Through InFO Vias (TIVs) and subsequent packaging steps, thereby eliminating the need for laser drilling and reducing manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If I/O pad density is increased to meet integration requirements, then more functions can be integrated into smaller areas, but packaging complexity and cost increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging architecture. Multiple semiconductor dies are vertically stacked and interconnected through through-silicon vias (TSVs), enabling high-density I/O connections in the vertical dimension rather than spreading pads across a large horizontal area. This dimensional change allows high I/O density while maintaining compact packaging complexity.
Solution Approach 2:
The patent implements nested packaging structures where multiple dies are stacked within a single package footprint. Each die contains functional circuits and I/O pads, and they are nested vertically with interconnect structures. This nesting approach achieves high I/O pad density by packing multiple functional units into a compact volume without proportionally increasing packaging complexity.
2Quantity of substance
If conventional packaging processes are used with high I/O pad density, then existing manufacturing capabilities are maintained, but production cost and complexity increase
Solution Approach 1:
The patent merges multiple manufacturing operations into integrated process steps. For example, TSV formation combines drilling, plating, and filling operations; die stacking combines bonding, alignment, and interconnection in a single assembly process. This merging reduces the total number of discrete manufacturing steps, lowering production cost and complexity while achieving high I/O pad density.
Solution Approach 2:
The patent performs preliminary actions during die fabrication before packaging. TSVs are formed and filled with conductive material during die manufacturing, and test structures are built-in beforehand. This preliminary preparation simplifies subsequent packaging operations, reducing overall production cost and complexity while enabling high I/O density interconnections.
3Manufacturing precision
If laser drill process is used for through via formation, then precise via holes can be created, but manufacturing complexity and cost increase
Solution Approach 1:
The patent replaces the laser drilling mechanical system with a mechanical drilling and electroplating system. Standard drilling equipment creates via holes with sufficient precision, followed by electroplating to form conductive walls and fill the vias. This substitution eliminates complex laser systems while achieving the required via hole precision through a simpler, more cost-effective manufacturing process.
Solution Approach 2:
The patent changes the formation parameters of through vias from laser-based thermal ablation to mechanical drilling with controlled dimensions. Via hole diameter, depth, and positioning are controlled through mechanical drilling parameters and subsequent electroplating thickness control. This parameter change enables precise via formation using conventional, less complex manufacturing equipment and processes.
Data Source
AI summary
Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.


