InFO Redistribution Layer Vias for Dense Semiconductor Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and miniaturization of semiconductor devices due to limitations in bonding processes and packaging techniques, particularly in forming efficient interconnects between stacked semiconductor devices.
Innovation Solution
The implementation of an ultra-high density redistribution layer interconnect in an integrated fan-out (InFO) package using a polymer layer with conductive vias and metallization layers, where vias are formed using a seed layer and electroplating processes to create a high-resolution, planarized surface for signal redistribution, allowing for more efficient integration of semiconductor devices in a smaller area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate seed layer sputtering and etching processes are used to form vias, then via formation reliability is improved, but manufacturing complexity and process time increase
Solution Approach 1:
The patent combines the seed layer formation and via etching processes into a single integrated step. The seed layer is deposited and patterned simultaneously with the via opening formation, eliminating the need for separate sputtering and etching processes. This integration maintains via formation reliability while significantly reducing manufacturing complexity and process time.
Solution Approach 2:
The seed layer is pre-formed and integrated with the via structure before final metallization. By preparing the seed layer as part of the via formation process itself rather than as a separate preliminary step, the patent streamlines the manufacturing sequence while ensuring reliable electrical connection for subsequent plating operations.
2Quantity of substance
If more vias are placed in a smaller area to increase integration density, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the dimensional parameters of the vias and their spacing to optimize density. By carefully controlling via diameter, depth, and center-to-center distance, the design achieves high integration density while maintaining manufacturable precision levels. The via geometry parameters are optimized to balance density with fabrication capabilities.
Solution Approach 2:
The patent utilizes the vertical dimension by forming deep, narrow vias that extend through multiple dielectric layers. This vertical exploitation allows increased via capacity in a given planar area without proportionally increasing lateral precision requirements, as the via density is managed through vertical stacking rather than purely lateral placement.
3Ease of manufacture
If conventional bonding processes are used for stacked semiconductor devices, then device assembly is simplified, but interconnect efficiency and signal distribution are limited
Solution Approach 1:
The patent segments the interconnect function into multiple distributed vias and metallization layers rather than relying on a single bonded interface. This segmentation allows signal redistribution to occur through a network of localized interconnects within the stacked structure, improving efficiency while maintaining modular assembly simplicity.
Solution Approach 2:
The patent transitions from planar signal distribution to three-dimensional interconnect architecture. By utilizing vertical vias and multiple metallization layers stacked in the Z-dimension, the design achieves efficient signal redistribution throughout the volumetric structure, overcoming the limitations of conventional two-dimensional bonding interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective, high-resolution signal redistribution and increased integration density by eliminating the need for separate seed layer sputtering and etching, reducing process windows, and allowing for more vias in a smaller area, thereby enhancing the miniaturization and efficiency of semiconductor devices.
Implementation Method 1
a seed layer is deposited over the via structure
Implementation Method 2
The via structure is then plated with a desired conductive material
Data Source
AI summary
In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.