Integrated Fan-Out Package Voltage Regulator Stacking

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Solution Overview

Problem

Integrated circuits, such as System-On-Chip (SOC) dies and Central Processing Units (CPU), require high stability and consumption of power, necessitating efficient voltage regulation, but existing technologies face challenges in minimizing power loss and optimizing voltage supply due to long metal lines and unbalanced layouts.

Innovation Solution

The development of an Integrated Fan-Out (InFO) package with voltage regulators, where VR dies are placed directly underlying the device dies, reducing metal line resistance and improving power efficiency by minimizing the distance to voltage regulators, and using conductive posts, through-vias, and redistribution lines for efficient interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If voltage regulators are placed far from device dies, then layout balance is improved, but metal line resistance increases and power efficiency deteriorates

Engineering Contradiction:
Improvelayout balanceVSAvoidpower efficiency
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The patent transitions from a planar layout to a three-dimensional stacked architecture, placing voltage regulators directly beneath device dies in the vertical dimension. This allows simultaneous achievement of short metal lines (improving power efficiency) and balanced layout (improving ease of operation) by utilizing the Z-axis for component placement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Instead of placing voltage regulators beside or above device dies in conventional layouts, the patent inverts the spatial relationship by positioning them directly underneath in the vertical direction. This inversion enables both short interconnect paths and symmetric distribution across the package footprint.

Inventive Principle:
Principle #13The other way round (Inversion)

2Area of stationary object

If metal lines are made longer to connect voltage regulators, then voltage supply coverage is improved, but voltage drop increases and power efficiency worsens

Engineering Contradiction:
Improvevoltage supply coverageVSAvoidvoltage drop
Core Design Contradiction:
Area of stationary objectVSLoss of energy

Solution Approach 1:

The patent uses vertical stacking to achieve wide voltage supply coverage without increasing horizontal metal line length. By placing multiple voltage regulators in different vertical layers beneath different device dies, the system covers large package areas while maintaining short interconnect paths and minimizing voltage drop.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the voltage supply function across multiple segmented voltage regulator modules distributed in the vertical stack. Each regulator serves a specific device die or region, providing localized voltage regulation that reduces overall voltage drop while maintaining comprehensive coverage through the segmented architecture.

Inventive Principle:
Principle #1Segmentation

3Loss of energy

If voltage regulators are integrated closer to device dies, then power efficiency is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvepower efficiencyVSAvoidpackage structure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements a nested doll architecture where voltage regulators are embedded within the vertical stack of device dies, with each layer containing functional components. This nesting achieves high integration and short interconnects while managing complexity through hierarchical organization, where each nested layer is independently designed and then integrated into the overall structure.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11063016B2Integrated fan-out package including voltage regulators and methods forming same
Publication Date: 2021.07.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11063016B2 patent drawing
  • US11063016B2 patent drawing
  • US11063016B2 patent drawing

AI summary

A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.