Information Flow Tracking for Integrated Circuit Fault Analysis
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Solution Overview
Problem
Current techniques for analyzing faults in integrated circuits are costly, time-intensive, and provide low-quality results, failing to ensure adequate fault coverage for safety-critical systems like automotive and aerospace systems.
Innovation Solution
The method involves using information flow tracking technology to analyze faults in integrated circuits by translating fault properties into an information flow model, automatically assigning label values, and optimizing hardware design to detect and prevent fault propagation, thereby enhancing fault tolerance verification coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual inspection of design files is used for fault analysis, then detailed examination can be performed, but the process becomes time-intensive and costly
Solution Approach 1:
The patent replaces manual inspection (mechanical human analysis) with an automated information flow tracking system that uses software algorithms to analyze hardware design files. This substitution maintains high fault detection accuracy while dramatically reducing analysis time and cost.
Solution Approach 2:
The patent introduces an intermediary information flow tracking system that acts as a bridge between the hardware design files and fault analysis. This intermediary automatically tracks how information flows through the design, identifying potential fault paths without requiring direct manual examination of every design detail.
2Productivity
If fault-simulation platforms are used for fault analysis, then automated analysis can be performed, but the fault coverage numbers are significantly reduced
Solution Approach 1:
Instead of simulating faults and observing their effects (traditional approach), the patent inverts the approach by tracking information flow forward through the design and identifying where faults could propagate. This reverse perspective enables more comprehensive fault coverage while maintaining automated analysis efficiency.
Solution Approach 2:
The information flow tracking system performs multiple functions simultaneously: it tracks data flow, identifies potential fault paths, and analyzes security vulnerabilities in a single unified framework. This multi-functionality achieves both high productivity and comprehensive fault coverage that single-purpose simulation platforms cannot achieve.
3Reliability
If comprehensive fault analysis is performed to ensure safety-critical system reliability, then fault coverage increases, but the cost and time requirements increase
Solution Approach 1:
The patent extracts and focuses analysis only on the critical information flow paths that could lead to faults or security vulnerabilities. By taking out and concentrating resources on these essential paths rather than analyzing every possible scenario, the system achieves comprehensive safety verification without overwhelming complexity.
Solution Approach 2:
The patent performs preliminary information flow tracking during the design analysis phase to identify potential fault paths before actual faults occur. This preliminary action enables proactive identification of safety issues, allowing designers to address them before fabrication, thereby ensuring reliability without requiring complex post-manufacturing testing.
Data Source
AI summary
The present disclosure includes systems and methods relating to information flow and analyzing faults in integrated circuits for digital devices and microprocessor systems. In general, one implementation, involves a technique including: receiving a hardware design specifying an implementation for information flow in a hardware configuration; receiving one or more labels annotating the hardware design; receiving one or more fault properties specifying at least a fault type relating to the one or more labels for implementing an information flow model indicating a fault path in the hardware configuration; determining, for each of the one or more fault properties, a label value by translating the fault property into the information flow model; and automatically assigning a respective label value to each of the one or more labels in the hardware design.