InGaZn Oxide Transistor Miniaturization via Selective Etching
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving miniaturization, stable electrical characteristics, high frequency performance, and low off-state current in transistors, particularly in integrating oxide semiconductors like In--Ga--Zn oxide into semiconductor devices.
Innovation Solution
A method for manufacturing semiconductor devices involves a series of etching and deposition steps using multiple conductors and insulators, including the formation of etching masks and subsequent etching processes to create a structure with specific layer thicknesses and compositions, particularly utilizing In--Ga--Zn oxide with indium, aluminum, gallium, or tin, to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor manufacturing methods are used, then manufacturing simplicity is maintained, but transistor miniaturization and performance improvement are limited
Solution Approach 1:
The manufacturing process is divided into multiple sequential steps including forming first and second conductors, creating etching masks, performing selective etching, and depositing insulating films. Each step contributes to the final miniaturized transistor structure, allowing precise control over dimensions and material properties while achieving complex three-dimensional architectures
Solution Approach 2:
The patent employs multi-layer stacking with insulating films (first insulator, second insulator, third insulator) and conductors arranged in different vertical and horizontal planes. This three-dimensional arrangement enables miniaturization by utilizing spatial dimensions beyond simple planar scaling, creating compact transistor structures with improved electrical characteristics
2Reliability
If oxide semiconductors are used to improve electrical characteristics, then field-effect mobility and frequency performance are enhanced, but manufacturing complexity increases
Solution Approach 1:
The transistor structure combines oxide semiconductor layers (containing In-Ga-Zn oxide) with conventional materials such as silicon-containing insulating films and metal conductors. This composite material approach leverages the high field-effect mobility of oxide semiconductors while maintaining compatibility with existing semiconductor manufacturing processes, achieving improved electrical characteristics without requiring complete process overhaul
Solution Approach 2:
The patent controls the composition and thickness of oxide semiconductor layers, adjusting parameters such as indium-gallium-zinc oxide ratios and layer thicknesses to optimize electrical characteristics. By precisely controlling these material parameters during deposition, the invention achieves high field-effect mobility and low off-state current while maintaining manufacturing feasibility
3Manufacturing precision
If multiple etching and deposition steps are performed to create miniaturized structures, then transistor performance is improved, but manufacturing time and process complexity increase
Solution Approach 1:
Etching masks are formed in advance before the actual etching of semiconductor layers. The first etching mask is created to define the first conductor pattern, and the second etching mask is prepared subsequently for the second conductor. This preliminary mask formation allows precise pattern transfer and controlled etching of thin layers, ensuring accurate layer thickness and positioning while streamlining the overall manufacturing sequence
Data Source
AI summary
A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.