Ingress Arbitration with Accelerated Header Memory for Lower Latency

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Solution Overview

Problem

Ingress arbitration in network switches incurs significant latency due to large packet memory buffers and complex linking data structures, especially when handling varying packet sizes and low bandwidth usage, leading to inefficient packet processing.

Innovation Solution

Implement a separate enqueuing and dequeuing pipeline using an accelerated memory for packet headers and a larger packet buffer for payloads, reducing latency by storing packet headers in a smaller, faster memory space when congestion is below a threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If large packet memory buffers and complex linking data structures are used to handle varying packet sizes, then the network switch can support high bandwidth capacities, but the latency for looking up packet header data fields increases significantly

Engineering Contradiction:
Improvepacket buffer sizeVSAvoidlookup latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments packet data into header portion and payload portion, storing them in separate memory locations. The header portion is stored in a first memory location while the payload portion is stored in a second memory location, allowing independent access to headers without traversing complex linking structures required for large payload data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a descriptor data structure that acts as an intermediary between the packet data and the memory system. The descriptor contains metadata including a pointer to the first memory location (header) and a second pointer to the second memory location (payload), enabling efficient indirect access to packet components without requiring direct traversal of large buffer structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If packet memory buffers of relatively large sizes are used to support buffering of varying packet sizes, then data loss is minimized, but the time latency for accessing packet data increases even when bandwidth usage is low

Engineering Contradiction:
Improvedata loss preventionVSAvoidaccess latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides packet storage into separate segments for headers and payloads, allowing the system to maintain large buffer capacities for reliability while accessing only the necessary header portion quickly through dedicated memory locations and descriptor pointers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary organization of packet data by storing headers and payloads in separately identified memory locations during the enqueue process. This preliminary arrangement enables rapid header access during dequeue operations without requiring traversal of the entire packet buffer structure, reducing access latency while maintaining buffer capacity.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If complex packet data linking structures are implemented to manage ingress traffic flows, then congestion and data loss are reduced, but the device complexity increases

Engineering Contradiction:
Improvecongestion managementVSAvoiddata structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the packet management system into distinct components: header storage in first memory locations, payload storage in second memory locations, and descriptor data structures that link them. This segmentation simplifies the overall structure by eliminating the need for complex nested linking structures while maintaining effective traffic flow management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The descriptor data structure serves as a simplified intermediary that contains essential metadata and pointers to packet components. This intermediary approach replaces complex linking structures with a straightforward descriptor-based system that is easier to manage and access while maintaining effective congestion control.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250267100A1Minimized latency ingress arbitration
Publication Date: 2025.08.21 MARVELL ASIA PTE LTD
  • US20250267100A1 patent drawing
  • US20250267100A1 patent drawing
  • US20250267100A1 patent drawing

AI summary

Techniques as described herein may be implemented to processing ingress packet traffic flows. A memory space that is divided into a packet buffer and an accelerated memory is defined. One or more congestion levels associated with ingress network traffic are determined. Upon enqueuing incoming packets, one or more memory locations are selected in the memory space for storing portions of each of the incoming packets based on at least one of the determined congestion levels.