Ingress Processor DMA for Out-of-Sequence Data
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Solution Overview
Problem
Existing RDMA technologies face challenges in integrating with embedded and automotive Ethernet environments due to large power requirements and difficulties in supporting specific protocols, which can lead to out-of-sequence data receipt and increased complexity.
Innovation Solution
A network device architecture that utilizes an ingress processor and storage controller to separate and sequence data units, employing a traffic monitor to send congestion notifications and pause data transfers when out-of-sequence data is detected, ensuring data is received in the correct order, thereby reducing power consumption and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RDMA protocols are used for direct memory access, then data exchange efficiency is improved, but power consumption increases
Solution Approach 1:
The patent segments the data exchange process into distinct phases: connection establishment, data transfer, and connection teardown. The ingress processor handles segmentation of incoming data units and reassembly in correct sequence, while the egress processor manages outgoing data. This segmentation allows efficient parallel processing without requiring full RDMA protocol stacks on both ends, reducing power consumption while maintaining high data exchange efficiency.
Solution Approach 2:
The patent introduces an intermediary mechanism using sequence numbers and buffering in the ingress processor to mediate between out-of-order received data units and the requirement for in-order processing. This intermediary approach enables efficient data flow without requiring complex hardware-assisted RDMA protocols, achieving good productivity with lower power consumption.
2Extent of automation
If hardware-assisted RDMA protocols are implemented, then direct memory access capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the essential direct memory access functionality from the complex RDMA protocol stack. The ingress processor directly accesses remote memory through simplified mechanisms, extracting only the necessary DMA capabilities while leaving out the complex protocol handling. This reduces device complexity while maintaining automation of memory access operations.
Solution Approach 2:
The system implements self-service through automatic sequence number tracking and out-of-order data reassembly in the ingress processor. The hardware automatically handles the reordering of data units without requiring complex protocol interpretation, achieving direct memory access capability with reduced device complexity.
3Speed
If data units are transmitted in parallel, then transfer speed is improved, but data sequence order may be disrupted
Solution Approach 1:
The patent applies preliminary action by assigning sequence numbers to data units before transmission. The ingress processor receives data units with embedded sequence numbers and uses these pre-assigned identifiers to reassemble data in the correct order, even when received out of sequence. This preliminary sequencing enables parallel high-speed transmission while maintaining data order stability.
Solution Approach 2:
The system uses feedback through sequence number comparison to detect out-of-order arrivals and triggers reassembly operations. The ingress processor continuously monitors sequence numbers and uses this feedback to maintain correct data ordering, enabling both high transfer speed and sequence stability.
Data Source
AI summary
A computer device in a network receives data units sent by a remote computer device over a network link in a sequenced order. A traffic monitor evaluates traffic on the network link, and selectively sends congestion notifications in response to determining that certain data units sent by the remote computer device have been received or will likely be received out of the sequenced order. The notifications cause the remote computer device to pause sending further data units. An ingress processor, separate from a central processing unit (CPU) of the computer device, detects a header segment of a received data unit and a corresponding payload segment of the received data unit. A storage controller stores the header segment of the received data unit in a first memory location, and stores the payload segment of the received data unit in a second memory location separate from the first memory location. The second memory location corresponds to a next location in a storage queue.