Inheritance-Aware Testbench Coverage Analysis for EDA
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Solution Overview
Problem
Existing electronic design automation (EDA) approaches fail to predict the number of simulations needed to achieve comprehensive coverage of integrated circuit designs, particularly with increasing testbench sizes and complex inheritance hierarchies, leading to incomplete device-under-test (DUT) coverage.
Innovation Solution
An automated inheritance aware analysis method is implemented to simulate electronic designs, generate coverage databases, and perform comprehensive coverage analysis of testbenches, identifying coverage holes and ensuring exhaustive coverage by independently exercising all user functions of base classes and their derived classes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If testbench size increases with more classes and methods to achieve comprehensive coverage, then coverage completeness improves, but analysis complexity and time consumption increase
Solution Approach 1:
The patent segments the testbench coverage analysis by separating base class coverage from derived class coverage. The system identifies and analyzes coverage holes in base classes independently, then tracks how derived classes exercise these base class functions. This segmentation transforms the complex hierarchical analysis into manageable discrete units that can be processed systematically.
Solution Approach 2:
The patent performs preliminary identification of base classes and their user functions before executing the full coverage analysis. By pre-processing the testbench structure to identify inheritance relationships and base class methods, the system prepares the analysis framework in advance, reducing the complexity of the actual coverage measurement process.
2Loss of information
If manual coverage analysis is performed to understand stimulus generation coverage, then coverage understanding improves, but time consumption and productivity decrease
Solution Approach 1:
The patent implements automated inheritance-aware analysis that performs coverage analysis independently without requiring manual intervention. The system automatically identifies base classes, traces derived class implementations, and generates coverage reports by itself, eliminating the need for manual code review while maintaining comprehensive coverage understanding.
Solution Approach 2:
The patent provides automated feedback through coverage reports that clearly identify coverage holes in base classes and track their exercise status in derived classes. This feedback mechanism enables verification engineers to quickly understand coverage status without manual analysis, improving both coverage understanding and verification efficiency.
3Reliability
If random fields and constraint rules are added to stimulus to improve test coverage, then stimulus comprehensiveness improves, but prediction capability of simulation needs deteriorates
Solution Approach 1:
The patent performs preliminary analysis of the testbench structure and inheritance hierarchy before simulations are executed. By pre-identifying base classes, user functions, and derived class relationships, the system establishes a baseline coverage model that can predict simulation requirements even as random fields and constraints are added, maintaining prediction capability amidst increasing test complexity.
Data Source
AI summary
The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test (“DUT”) and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and testbench using an automated inheritance aware analysis and applying the coverage analysis results to the testbench after simulation.