Inhibitor Layer for Damascene Electroplating

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Solution Overview

Problem

The process of single damascene or dual-damascene electroplating for large semiconductor structures faces challenges with thick metal overburden on planar surfaces, leading to lengthy chemical mechanical polishing (CMP) or etching times, which are costly and unfavorable for volume manufacturing.

Innovation Solution

A method involving the formation of a barrier layer, seed layer, and inhibitor layer, where the inhibitor layer is selectively removed to expose the seed layer, allowing for controlled electroplating within the damascene features while preventing deposition on the inhibitor layer, followed by CMP or etching to planarize the structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If single damascene or dual-damascene electroplating is used for large semiconductor structures, then metal lines and vias can be formed, but thick metal overburden is deposited on planar surfaces outside the damascene feature

Engineering Contradiction:

Improvemetal deposition controlVSAvoidmetal overburden thickness

Core Design Contradiction:

Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent applies local quality by using an inhibitor layer with spatially varying properties - the inhibitor layer has different inhibitor concentrations in different regions, with higher inhibitor concentration at periphery regions and lower inhibitor concentration at center regions, enabling selective suppression of metal deposition in specific areas while allowing deposition in others

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The inhibitor layer acts as an intermediary between the seed layer and the electroplating process, mediating the metal deposition by selectively preventing metal accumulation on planar surfaces while allowing controlled deposition within damascene features through the patterned removal of the inhibitor layer

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If thick metal overburden is present on planar surfaces, then complete coverage is achieved, but long CMP or etching times are required to remove and planarize the metal

Engineering Contradiction:

Improvesurface planarizationVSAvoidCMP or etching time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing inhibitor layer removal before the electroplating process, creating a pre-configured surface where the inhibitor layer is selectively removed from damascene features while remaining on planar surfaces, so that subsequent metal deposition occurs only in desired areas without forming excessive overburden

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The inhibitor layer provides preliminary anti-action by preemptively preventing metal deposition on planar surfaces during the electroplating process, counteracting the tendency of metal to accumulate everywhere and thereby eliminating the need for lengthy removal processes

Inventive Principle:

Principle #9Preliminary anti-action

3Manufacturing precision

If long CMP or etching times are used to remove metal overburden, then planarization is achieved, but manufacturing cost increases

Engineering Contradiction:

Improvesurface planarizationVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by configuring the inhibitor layer with spatially varying properties before electroplating, so that the subsequent metal deposition process inherently produces minimal overburden, eliminating the need for expensive and time-consuming corrective CMP or etching processes

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the need for extensive CMP or etching, shortening processing times and lowering costs by ensuring precise metal deposition and planarization, thus enhancing the efficiency and cost-effectiveness of semiconductor manufacturing.

Implementation Method 1

single damascene or dual-damascene electroplating of large structures

Methodology Applied

Scientific EffectElectroplating: Electroplating

Implementation Method 2

extremely long chemical mechanical polishing (CMP) or etching times to remove and planarize the metal overburden

Methodology Applied

Scientific EffectChemical mechanical polishing:

Implementation Method 3

extremely long chemical mechanical polishing (CMP) or etching times to remove and planarize the metal overburden

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS8786085B2Semiconductor structure and method for making same

Publication Date: 2014.07.22 INFINEON TECHNOLOGIES AG

AI summary

One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.