Initialization Core Reset Logic for Multi-Core Processor Stability
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Solution Overview
Problem
In multi-core processing systems, efficiently resetting a problematic core while maintaining operation of at least one other core is challenging due to the complexity of communication paths and the need to minimize space on the chip, especially when core availability changes during operation.
Innovation Solution
An initialization core with reset logic detects unresponsive cores, broadcasts messages to stop requests, and generates packets to initiate and manage the reset and unreset of problematic cores, allowing continued operation of other cores without resetting them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset mechanism is implemented to reset a problematic core, then system reliability is improved, but device complexity increases due to the need for reset logic and communication protocols
Solution Approach 1:
An initialization core acts as an intermediary to manage reset operations. When a core becomes unresponsive, the initialization core detects the issue and coordinates the reset process by sending packets through the interconnect network, rather than requiring each core to have independent reset capabilities. This mediator approach improves reliability while minimizing the complexity added to individual cores.
Solution Approach 2:
The reset mechanism uses universal packets that can be sent through the existing interconnect network (mesh, ring, or peer-to-peer) to reach any core. The same communication infrastructure used for normal operation is also used for reset commands, eliminating the need for dedicated reset hardware paths and reducing overall device complexity.
2Area of stationary object
If communication paths between cores are minimized to save space, then chip area is reduced, but the difficulty of detecting and measuring core status increases
Solution Approach 1:
The existing interconnect network (mesh, ring, or peer-to-peer) serves dual purposes: normal data communication and status detection/reset signaling. By using the same communication paths for both purposes, the patent eliminates the need for separate detection hardware, reducing chip area while maintaining the ability to detect unresponsive cores through packet response monitoring.
Solution Approach 2:
The system uses feedback mechanisms where the initialization core sends packets to target cores and monitors for responses. If a core is unresponsive, the lack of feedback (no response packet) detects the problem. This feedback-based detection works efficiently within the minimized communication paths, as it leverages the normal communication infrastructure rather than requiring additional detection circuits.
3Reliability
If all cores are reset when one core becomes problematic, then system reliability is improved, but productivity decreases due to disruption of other operating cores
Solution Approach 1:
The reset operation is segmented to affect only the specific problematic core rather than all cores. The initialization core identifies the unresponsive core address and sends reset packets only to that specific core through the interconnect network. This segmentation allows other cores to continue operating normally, maintaining productivity while still improving reliability by isolating and resetting only the faulty component.
Solution Approach 2:
The reset mechanism applies local quality by targeting specific cores based on their individual status. Instead of a global reset, the system applies reset operations locally to only those cores that are unresponsive, as identified by the initialization core through packet communication. This localized approach preserves the functionality of healthy cores while addressing problematic ones, balancing reliability and productivity.
Data Source
AI summary
This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.