Non-Volatile Memory Programming Voltage Setting Without Voltage Spikes

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Solution Overview

Problem

Existing semiconductor memory technologies face challenges in optimizing the design of memory structures and peripheral circuitry, leading to restricted area availability and differing processing technologies, which affect performance and scalability.

Innovation Solution

The solution involves separating memory structures and peripheral circuitry onto separately formed dies, allowing for optimized manufacturing processes and increased space for additional capabilities, using bonded multi-die memory circuits with a memory die and a control die, optimized for NMOS and CMOS technologies respectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If memory structures and peripheral circuitry are integrated on the same die, then device complexity is reduced, but area availability is restricted and manufacturing flexibility is limited

Engineering Contradiction:

Improvedevice complexityVSAvoidarea availability

Core Design Contradiction:

Device complexityVSArea of stationary object

Solution Approach 1:

The patent divides the memory system into separate dies: one die for memory structures and another die for peripheral circuitry. This segmentation allows each die to be optimized independently for its specific function, increasing area availability on each die while maintaining overall system integration through bonding.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If memory structures and peripheral circuitry are integrated on the same die, then device complexity is reduced, but manufacturing flexibility and optimization are limited

Engineering Contradiction:

Improvedevice complexityVSAvoidmanufacturing flexibility

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different manufacturing optimizations to different parts of the system. Memory structures on one die can be optimized for NMOS technology while peripheral circuitry on another die can be optimized for CMOS technology, allowing each region to have the most appropriate manufacturing process for its specific requirements.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If separately formed dies are used for memory structures and peripheral circuitry, then area utilization and manufacturing optimization are improved, but device complexity increases

Engineering Contradiction:

Improvearea utilizationVSAvoiddevice complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent combines separately formed dies into a single integrated memory circuit through bonding. This merging allows the system to benefit from the area utilization and manufacturing optimization of separate dies while presenting an integrated solution that minimizes the increase in overall device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12456535B2Non-volatile memory with efficient setting of initial program voltage

Publication Date: 2025.10.28 SANDISK TECHNOLOGIES LLC

AI summary

While programming a first set of memory cells, a non-volatile memory apparatus determines an initial magnitude of a programming signal for a second set of memory cells based on testing during the programming of the first set of memory cells. The testing comprises sensing at a first test voltage level and sensing at a second test voltage level without apply a voltage spike between the two sensing operation. Removing the voltage spike results in a performance increase (i.e. faster programming speed) and as well as a decrease in power usage.