Initiative Wear Leveling for Non-Volatile Memory Blocks

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Solution Overview

Problem

Non-volatile memory, such as flash memory, experiences uneven wear due to varying write cycles, leading to premature failure in heavily used portions, which can be mitigated by implementing a wear leveling process to distribute write operations more evenly.

Innovation Solution

The implementation of an initiative wear leveling process that exchanges data between groups of most worn and least worn memory blocks, utilizing physical and logical block erase counts to identify and swap blocks, thereby balancing the number of erase-write cycles across the memory device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If wear leveling process is implemented to distribute write operations evenly, then memory lifespan is extended, but device complexity increases

Engineering Contradiction:
Improvememory lifespanVSAvoiddevice complexity
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The patent maintains erase count information for each memory block in advance, before wear leveling is needed. This preliminary tracking of erase counts allows the system to identify worn blocks and perform wear leveling operations proactively, extending memory lifespan while managing complexity through pre-organized data structures

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where erase count information is continuously monitored and used to trigger wear leveling operations. When erase counts indicate uneven wear distribution, the system automatically initiates remapping operations to redistribute data, creating a closed-loop control system that extends memory life through adaptive management

Inventive Principle:
Principle #23Feedback

2Productivity

If remapping operations are performed frequently to maintain even wear distribution, then memory performance is maintained, but loss of time increases

Engineering Contradiction:
Improvememory performanceVSAvoidloss of time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs remapping operations selectively based on erase count thresholds rather than continuously. By triggering wear leveling only when uneven wear exceeds certain thresholds, the system maintains adequate memory performance while minimizing the time lost to remapping operations, avoiding unnecessary interventions

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8356152B2Initiative wear leveling for non-volatile memory
Publication Date: 2013.01.15 INTEL NDTM US LLC
  • US8356152B2 patent drawing
  • US8356152B2 patent drawing
  • US8356152B2 patent drawing

AI summary

A method and apparatus for initiative wear leveling for non-volatile memory. An embodiment of a method includes counting erase cycles for each of a set of multiple memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including incrementing a first count for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count for a logical block address of the memory block. The method also includes determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks.