Initiator Clock Enable Signals for Flexible Bus Data Transfer
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Solution Overview
Problem
Current data processing systems, such as those using the AXI bus, are limited by allowing only integer ratios of clock frequencies between masters and slaves, restricting the flexibility and performance of data communication.
Innovation Solution
The introduction of two distinct clock enable signals, an initiator output enable signal and an initiator input enable signal, allows for intermediate clock ratios, enabling more flexible communication between devices with different frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single clock enable signal is used to control data transmission frequency, then the system maintains simplicity and backwards compatibility, but the flexibility in clock frequency ratios is limited to integer values only
Solution Approach 1:
The single clock enable signal is segmented into two separate signals: an output enable signal for controlling data output from the master, and an input enable signal for controlling data input to the master. This segmentation allows independent control of data transmission and reception, enabling intermediate clock ratios while maintaining system functionality.
Solution Approach 2:
The patent introduces dynamic control of clock enable signals with different periods. The output enable signal has a period corresponding to the master clock frequency, while the input enable signal has a period corresponding to the slave clock frequency. This dynamic adjustment allows the system to adapt to different clock frequency ratios, including half-integer ratios, thereby increasing flexibility.
2Productivity
If integer ratios of clock frequencies are enforced between master and slave, then the system maintains simplicity in signal generation, but the performance requirements are limited
Solution Approach 1:
The patent changes the parameter of clock enable signal periods to match the respective clock frequencies of master and slave devices. By adjusting the periods of the output enable and input enable signals to correspond to the master and slave clock frequencies respectively, the system achieves accurate data synchronization at intermediate clock ratios, improving communication performance.
3Adaptability or versatility
If two distinct clock enable signals are introduced, then intermediate clock ratios are supported and flexibility is increased, but additional signals are required
Solution Approach 1:
The two clock enable signals serve multiple functions: they control data transmission and reception independently, support intermediate clock ratios, and maintain backwards compatibility with single-signal systems when clock ratios are integer values. This multi-functionality justifies the addition of the second signal.
Solution Approach 2:
The patent uses the two clock enable signals as intermediaries between the master and slave devices, mediating the frequency difference and enabling reliable data communication at intermediate clock ratios. These signals act as the mediator that coordinates the different timing rates without requiring direct frequency conversion.
Data Source
AI summary
A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configured to output signals that are different to each other.