Injected PLL Offset Calibration for Clock Spur Elimination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional reference clock signal injected phase locked loop circuits suffer from significant phase mismatch issues, resulting in large clock spurs that limit their application due to uncalibrated phase differences between the reference clock signal and the voltage controlled oscillator output.
Innovation Solution
The proposed solution integrates an offset calibration loop within the phase locked loop circuit, utilizing a state machine to disconnect and reconnect loops for precise calibration of the phase detector, ensuring zero phase offset and aligning the reference clock signal injection path with the phase detection path, thereby eliminating clock spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a reference clock signal is directly injected into the phase locked loop without disconnecting the voltage controlled oscillator, then the reference clock signal can be injected into the loop, but a phase difference exists between the reference pulse and the VCO output signal, resulting in extremely large clock spurs
Solution Approach 1:
The patent applies preliminary action by implementing an offset calibration loop that calibrates the phase detector offset before the reference clock signal is injected into the main PLL. The calibration process adjusts the phase detector to eliminate phase differences between the reference pulse and VCO output signal, ensuring that when the reference clock signal is subsequently injected, no large clock spurs are generated. This preliminary calibration action prevents the harmful effect before it can occur during normal operation.
2Adaptability or versatility
If the phase difference between reference pulse and VCO output signal is large, then the reference clock signal can be injected, but the clock spur increases significantly (e.g., 31.8 dBc at 10 μs phase difference)
Solution Approach 1:
The patent implements feedback through an offset calibration loop that continuously monitors and adjusts the phase detector offset. The calibration process uses feedback from the phase detector to automatically adjust and minimize the phase difference between the reference pulse and VCO output signal. This feedback mechanism ensures high phase matching precision (reducing clock spur to 52 dBc at 1 ps phase difference) while maintaining the ability to inject the reference clock signal into the PLL.
3Object-generated harmful factors
If an offset calibration loop is added to calibrate the phase detector, then phase mismatch problems are solved and clock spurs are eliminated, but the circuit complexity increases
Solution Approach 1:
The patent applies merging by integrating the offset calibration loop with the main PLL circuitry. The calibration loop shares common components such as the phase detector, voltage controlled oscillator, and feedback paths with the main PLL. By merging the calibration function into the existing PLL structure rather than adding completely separate calibration hardware, the patent eliminates clock spurs while minimizing the increase in overall circuit complexity.
Data Source
AI summary
The present disclosure provides a reference clock signal injected phase locked loop circuit and an offset calibration method. The reference clock signal injected phase locked loop circuit includes a first pulse generator, a second pulse generator, a state machine, a pulse selection and amplification circuit, a voltage controlled delay line, a phase detector, and a filter, and forms an offset calibration loop, a phase locked loop, a voltage controlled oscillator loop, and an injection locked loop. The state machine disconnects the phase locked loop and the voltage controlled oscillator loop and enables the offset calibration loop to calibrate the phase detector; the state machine enables the phase locked loop and the voltage controlled oscillator loop and locks a signal of the second pulse generator; and the state machine enables the injection locked loop for injecting a first pulse signal of the first pulse generator.