Injection-Locked Multi-Phase Clock Generator With Lower Phase Noise
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Solution Overview
Problem
Conventional multi-phase clock generators using Phase Locked Loops (PLLs) are susceptible to phase noise due to the sensitivity of voltage-controlled oscillators to power supply and substrate interference, leading to instability and noise issues.
Innovation Solution
A multi-phase clock generator employing injection locking with a loop oscillator comprising CMOS phase inverters, an RC filter, and a bias current source, which isolates the clock input signal from the bias current source and tail current sources, eliminating the need for a phase detector and charge pump, thereby reducing phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Phase Locked Loop (PLL) is used to generate multi-phase clock signals, then phase control and synchronization can be achieved, but the voltage-controlled oscillator becomes sensitive to power supply and substrate interference, resulting in phase noise and instability
Solution Approach 1:
The patent extracts and removes the voltage-controlled oscillator from the system, replacing it with a ring oscillator that is insensitive to power supply and substrate interference. This eliminates the source of phase noise while maintaining the phase control functionality through a different mechanism.
Solution Approach 2:
The patent introduces an injection locking mechanism as an intermediary between the reference clock and the ring oscillator. This mediator allows the ring oscillator to lock to the reference frequency without requiring a sensitive voltage-controlled oscillator, thereby achieving phase synchronization without the associated noise problems.
2Reliability
If a Delay Locked Loop (DLL) is used to generate multi-phase clock signals, then smaller jitters and less noise can be achieved, but phase noise is inevitable due to the usage of the charge pump
Solution Approach 1:
The patent removes the charge pump from the system entirely, replacing the DLL architecture with an injection-locked ring oscillator. This extraction eliminates the primary source of phase noise (the charge pump) while maintaining the multi-phase clock generation capability through the inherent phase division of the ring oscillator structure.
Solution Approach 2:
The patent uses multiple identical CMOS phase inverters connected in a loop to create N different phase outputs. This copying approach generates multiple clock phases simultaneously without requiring a charge pump, achieving the same functional result with a fundamentally different and quieter mechanism.
3Ease of operation
If a voltage-controlled oscillator is used in the PLL, then phase control can be implemented, but the oscillator becomes very sensitive to interference and noise from the power supply or substrate
Solution Approach 1:
The patent replaces the voltage-controlled oscillator (an electronic system sensitive to electrical interference) with an injection-locked ring oscillator. This substitution maintains the phase control capability through injection locking while eliminating the sensitivity to power supply and substrate noise that plagues voltage-controlled oscillators.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces phase noise by relying on the noise floor of the input signal, eliminating mismatch and load asymmetry, resulting in improved spur characteristics and stability compared to traditional DLLs.
Implementation Method 1
The loop oscillator outputs a clock output signal whose frequency is the same as a frequency of the clock input signal inputted by the frequency injection source under the effect of injection locking
Data Source
AI summary
Embodiments provide a multi-phase clock generator. The clock generator includes a loop oscillator, a RC filter, a bias current source and a frequency injection source. The loop oscillator includes N levels of CMOS phase inverters which are connected in series and form a loop, N represents an odd number greater than 1. The N levels of CMOS phase inverters have the same structures, each of which includes a CMOS phase inverter main body and a tail current source which is a current mirror of the bias current source. As an effect of RC filter, a clock input signal inputted by the frequency injection source is applied to the first level tail current source, while other tail current sources are not influenced. Injection locking is induced, such that phase noise and frequency stray can be reduced.