Injection-Locked Clock Multiplier for Fast Frequency Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase-locked loop (PLL) multipliers incur long re-lock times after frequency changes, while injection-locked oscillators offer fast lock times but with limited frequency agility, posing challenges for frequency-agile clocking in integrated circuits.
Innovation Solution
Implementing a bank of multiplying injection-locked oscillators (MILOs) with spectrally-staggered lock ranges operated in parallel to achieve fast locking and a wide input frequency range, along with a flexible-injection-rate oscillator that seamlessly transitions between different injection pulse rates to support broad frequency agility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional phase-locked loop (PLL) multipliers are used, then broad input frequency range is achieved, but long re-lock times incur latency penalties
Solution Approach 1:
The patent divides the frequency multiplication function into multiple parallel injection-locked oscillators, each tuned to a specific frequency multiple (e.g., 2x, 3x, 4x). This segmentation allows the system to avoid re-locking by simply switching between pre-tuned oscillators, thereby resolving the contradiction between broad frequency range and fast response time.
Solution Approach 2:
The injection-locked oscillators are pre-tuned to specific frequency multiples before operation. When a frequency change is required, the system switches to a pre-configured oscillator rather than re-locking, which eliminates the latency penalty associated with conventional PLL multipliers.
2Loss of time
If injection-locked oscillators are used, then fast lock times are achieved, but narrow input frequency range limits frequency agility
Solution Approach 1:
The patent merges multiple injection-locked oscillators with different frequency multiplication factors into a single system. By combining oscillators tuned to 2x, 3x, 4x, and other multiples, the system achieves both fast lock times (inherent to injection-locked oscillators) and a broad effective input frequency range (achieved by switching between oscillators).
3Use of energy by moving object
If frequency switching is implemented in mobile devices, then power consumption is reduced, but latency is incurred during frequency transitions
Solution Approach 1:
The system pre-configures multiple injection-locked oscillators with different frequency multiplication factors. During frequency transitions, the system switches between pre-configured oscillators rather than re-locking, which eliminates transition latency while maintaining the power-saving benefits of frequency switching in mobile devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low-latency, frequency-agile clock multipliers with fast locking and wide input frequency range, reducing power consumption and latency in mobile devices.
Implementation Method 1
multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel
Data Source
AI summary
In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.