Injection-Locked Clock Multiplier for Fast Wide-Range Frequency Switching

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Solution Overview

Problem

Conventional phase-locked loop (PLL) multipliers incur significant latency during frequency changes, while injection-locked oscillators offer fast lock times but with limited frequency agility, making them unsuitable for frequency-agile systems that require both low latency and wide frequency range.

Innovation Solution

A frequency-agile clock generator using multiple injection-locked oscillators with staggered lock ranges operates in parallel to achieve fast locking and a broad input frequency range, with a flexible-injection-rate oscillator that seamlessly transitions between different injection pulse rates to support various frequency operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional phase-locked loop (PLL) multipliers are used, then broad input frequency range is achieved, but significant latency is incurred during frequency changes

Engineering Contradiction:
Improveinput frequency rangeVSAvoidlatency during frequency changes
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent divides the frequency multiplication function into multiple parallel injection-locked oscillators, each optimized for a specific frequency range. This segmentation allows the system to switch between oscillators for different frequency needs, achieving both broad range and fast response without the latency of PLL re-locking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects and switches between multiple injection-locked oscillators based on the desired output frequency. This dynamic switching mechanism enables rapid frequency changes without the re-lock latency inherent in conventional PLLs, as each oscillator is already prepared and stable in its designated frequency range.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If injection-locked oscillators are used, then fast lock time is achieved, but narrow input frequency range is incurred

Engineering Contradiction:
Improvelock timeVSAvoidinput frequency range
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The frequency range is segmented into multiple overlapping ranges, with each injection-locked oscillator optimized for a specific segment. This allows the system to maintain fast lock characteristics within each segment while collectively covering a broad overall frequency range through the bank of oscillators.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a universal frequency multiplication system where a bank of injection-locked oscillators collectively performs the function that a single oscillator cannot achieve alone. Each oscillator is a specialized component, but together they provide universal frequency coverage with fast locking characteristics.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If multiple injection-locked oscillators with staggered lock ranges operate in parallel, then broad input frequency range and fast locking are achieved, but device complexity increases

Engineering Contradiction:
Improveinput frequency rangeVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The complex frequency multiplication task is segmented into multiple simpler, identical injection-locked oscillator units. Each unit is relatively simple in design, but their parallel arrangement achieves the complex overall function of broad-range, fast frequency multiplication with manageable individual component complexity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables low-latency, frequency-agile clock multipliers with broad input frequency range and low power consumption, addressing the limitations of conventional PLLs and injection-locked oscillators by providing rapid frequency switching without latency penalties.

Implementation Method 1

multiple injection-locked oscillators with staggered lock ranges operates in parallel to achieve fast locking and a broad input frequency range

Methodology Applied
Scientific EffectInjection locking:

Data Source

PatentUS10951218B2Multi-mode clock multiplier
Publication Date: 2021.03.16 RAMBUS INC
  • US10951218B2 patent drawing
  • US10951218B2 patent drawing
  • US10951218B2 patent drawing

AI summary

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.