Injection-Locked PLL Duty-Cycle Correction for Low Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ring-based PLLs suffer from increased jitter and challenges in deep sub 50 nm technology due to high noise and frequency drift, making it difficult to correct frequency errors while suppressing phase errors, especially when using injection locking.
Innovation Solution
A duty-cycle calibration circuit is implemented to correct timing errors in injection-locked PLLs by obtaining patterns of error pulses, multiplying them with a duty-cycle distortion template, and using the resulting correction signal to control a digitally controlled delay line, thereby compensating for duty-cycle variations in the reference clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If injection locking is used to suppress phase errors, then phase noise is reduced, but frequency errors cannot be corrected because injection locking masks frequency errors
Solution Approach 1:
The patent implements periodic suppression of injection-locking pulses at specific phases (e.g., every other cycle or at designated phase intervals) to create windows where frequency correction can occur without interference from concurrent phase adjustments. This periodic action allows the system to alternate between phase suppression mode and frequency correction mode, resolving the contradiction by enabling both functions at different times rather than simultaneously
Solution Approach 2:
The system performs frequency correction in advance during periods when injection locking is suppressed, before phase suppression becomes active again. By preliminarily correcting frequency errors during the suppression windows, the system ensures that when injection locking resumes, both phase and frequency are already optimized, eliminating the masking effect on frequency error detection
2Area of stationary object
If ring-based PLLs are used instead of LC-based PLLs, then area is reduced, but jitter increases due to high noise and frequency drift
Solution Approach 1:
The patent implements a dual-loop feedback structure with separate phase-tracking and frequency-tracking paths. The phase-tracking path uses injection locking to suppress phase noise, while the frequency-tracking path independently corrects frequency drift. This feedback architecture allows the compact ring oscillator to achieve LC-like jitter performance by continuously correcting both phase and frequency errors without requiring large inductor-capacitor components
Solution Approach 2:
The system introduces a gating mechanism as an intermediary that selectively enables or disables injection-locking pulses based on the operational phase. This mediator coordinates between the phase suppression function and frequency correction function, allowing the ring oscillator to benefit from both injection locking's phase noise reduction and frequency tracking's drift correction, thereby achieving low jitter in a compact area
3Measurement precision
If duty-cycle distortion correction is applied, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses a digital copy of the reference clock signal to generate the duty-cycle correction signal, rather than requiring complex analog circuitry. By duplicating and processing a digital version of the reference signal through simple logic operations (XNOR gates and delay elements), the system achieves timing accuracy improvement without proportionally increasing device complexity
Solution Approach 2:
The system corrects duty-cycle distortion by changing the timing parameters of correction pulses rather than redesigning the entire clock generation architecture. By adjusting pulse widths, delays, and phases through simple digital control, the system improves timing accuracy while maintaining relatively low complexity compared to analog duty-cycle correction approaches
Data Source
AI summary
We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.