Injection-Locked PLL Frequency Synthesizer for Fast Locking
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Solution Overview
Problem
Conventional frequency synthesizers require a long time for frequency locking and have high power consumption due to their complex structure, which includes multiple blocks and the need for alternately using dividers with division ratios of N and N+1 to achieve decimal frequencies.
Innovation Solution
A frequency synthesizer circuit is separated into a frequency synthesizer part and an injection locked PLL part, where the frequency synthesizer performs a frequency and phase lock operation using a fractional number and a first reference clock, and the injection locked PLL starts a frequency lock operation after being reset, multiplying the second reference clock by an integer multiple to output a high-frequency clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional frequency synthesizer uses a fractional-N PLL with DSM to generate decimal frequencies, then arbitrary frequency control is achieved, but frequency locking time becomes quite long
Solution Approach 1:
The frequency synthesizer is divided into two independent parts: a frequency synthesizer circuit that generates a low-frequency output clock, and an injection-locked PLL circuit that multiplies this clock to generate the final high-frequency output. This segmentation allows each circuit to be optimized for its specific function, with the injection-locked PLL providing fast frequency locking while the frequency synthesizer provides precise frequency control.
2Adaptability or versatility
If a conventional frequency synthesizer includes multiple blocks for fractional frequency synthesis, then decimal frequency output is achieved, but power consumption is increased
Solution Approach 1:
The invention extracts the frequency multiplication function from the conventional frequency synthesizer structure and implements it separately using an injection-locked PLL circuit. This allows the main frequency synthesizer to operate at lower power while the injection-locked PLL, which is more power-efficient for frequency multiplication, handles the frequency boosting to achieve the final output frequency.
Solution Approach 2:
The invention combines a frequency synthesizer circuit with an injection-locked PLL circuit to create a hybrid architecture. The frequency synthesizer provides precise frequency control and the injection-locked PLL provides efficient frequency multiplication, achieving both decimal frequency generation and low power consumption through the synergistic combination of these two circuits.
Data Source
AI summary
The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit part and an injection locked PLL circuit part and sequentially performing a frequency synthesizer lock operation and an injection lock operation to implement fast frequency and phase locking. The present invention comprises: a frequency synthesizer configured to perform a frequency and phase lock operation according to fractional number information and a first reference cock signal supplied from outside and thereby output a reset signal and a second reference clock signal; and an injection locked PLL configured to start a frequency lock operation after being reset by the reset signal inputted when the frequency synthesizer is frequency-locked, receive the second reference clock signal as a reference clock, multiply the second reference clock signal by an integer multiple of target frequency, and output an output clock signal.