Injection-Locked PLL Phase Adjustment for Low-Jitter Clock Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in quickly correcting phase errors due to noise, leading to increased jitter and difficulty in maintaining synchronization at high data rates, especially as the distance between computing nodes increases and data rates become faster.
Innovation Solution
A phase-modification circuit utilizing a master oscillator and auxiliary oscillators with an injection-locking mechanism that selectively couples an auxiliary signal to the master oscillator, allowing for continuous phase error correction within a half period of the divided reference clock, thereby reducing jitter and improving phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional phase-locked loop is used to correct phase errors, then phase synchronization is achieved, but the correction time is long (several loop time constants) and jitter increases
Solution Approach 1:
The patent pre-charges capacitor nodes to specific voltage levels (e.g., VDD/2) before the actual phase correction event. This preliminary preparation allows the phase correction to occur rapidly when needed, rather than building up correction capability over time. The pre-charged nodes are ready to immediately influence the oscillator phase when activated, eliminating the need for gradual accumulation over multiple loop time constants.
Solution Approach 2:
The patent employs periodic clock signals (e.g., divided reference clock) to periodically update and reset the phase correction mechanism. This periodic action ensures that the phase correction capability is refreshed regularly, allowing for rapid response to phase errors while maintaining stability. The periodic nature enables the system to correct phase errors within a fraction of a clock period rather than requiring continuous gradual adjustment.
2Speed
If phase correction strength is increased to reduce correction time, then phase alignment speed improves, but dither increases during stable operation
Solution Approach 1:
The patent applies partial correction action by only activating the phase correction mechanism when phase errors are detected, rather than continuously applying maximum correction strength. The pre-charged capacitor nodes provide just enough correction influence to rapidly reduce phase errors without over-correcting or introducing excessive dither during stable operation. This selective partial action maintains both speed and stability.
Solution Approach 2:
The patent dynamically changes the effective correction strength by controlling the timing and duration of capacitor discharge events. Rather than using a fixed high correction strength, the system adjusts the correction parameter (discharge timing) based on the detected phase error magnitude and direction. This allows rapid correction when needed while minimizing disturbance during stable operation.
3Productivity
If data rate is increased to improve system performance, then communication speed improves, but the data eye shrinks and phase alignment constraints become tighter
Solution Approach 1:
The patent pre-charges the capacitor nodes to precise voltage levels (e.g., VDD/2) in advance, creating a ready-to-fire correction mechanism that can immediately adjust the oscillator phase when phase errors are detected. This preliminary preparation enables the system to maintain precise phase alignment even at high data rates where the data eye is narrow, because the correction action is instantaneous rather than gradual.
Solution Approach 2:
The patent replaces the traditional gradual mechanical-like adjustment of phase (through continuous voltage control over multiple loop time constants) with an instantaneous electrical discharge mechanism. The pre-charged capacitors can be discharged almost instantly to provide rapid phase correction, substituting the slow continuous control mechanism with a fast discrete action that is suitable for high-speed communication where the data eye is narrow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The phase-modification circuit effectively reduces both absolute peak jitter and cycle-to-cycle jitter, enabling high-speed communication links and increasing the number of available channels, while maintaining high energy efficiency and improving PLL performance.
Implementation Method 1
an injection-locking mechanism that selectively couples the auxiliary signal to the master oscillator to continuously correct a phase error of the output clock relative to the divided reference clock
Data Source
AI summary
A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.