Inkjet Chip Ejection Orifice Array Formation via Multi-Step Exposure

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Solution Overview

Problem

The existing process for producing ink jet recording head chips faces challenges in achieving accurate and efficient formation of ejection orifice arrays due to lens aberrations, leading to color unevenness in printing, especially when the field angle of the reticle is utilized to its limits, causing distortion in the exposure pattern and resulting in deviations in the position of ejection orifices.

Innovation Solution

A process involving multiple reduction projection exposures on a wafer with a photosensitive resin layer, where the reticle is moved relative to the wafer to form ejection orifice array patterns, allowing for the formation of chips with aligned ejection orifice arrays, reducing the total pitch difference and minimizing color unevenness by using a reticle with specific exposure patterns that account for line symmetry and center alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If reduction projection exposure is conducted to form ejection orifice arrays using a reticle, then productivity is improved by batch processing multiple chips, but lens aberrations cause distortion in the exposure pattern at the margin of the field angle, leading to deviations in ejection orifice positions

Engineering Contradiction:
Improvebatch processing efficiencyVSAvoidejection orifice position accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The exposure process is divided into multiple steps, with the first exposure forming a first ejection orifice array pattern and the second exposure forming a second ejection orifice array pattern. This segmentation allows each exposure to be optimized independently, reducing the impact of lens aberrations on overall pattern accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different exposure conditions to different regions of the reticle. The first ejection orifice array pattern is formed using light from a first region of the reticle, while the second pattern uses light from a second region. This local quality approach ensures that each region's exposure is optimized for its specific location, compensating for field angle variations and lens aberrations.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the field angle of the reticle is utilized to its limits to arrange patterns near the margin, then the area per chip increases allowing more ejection orifice arrays, but lens aberrations greatly affect the finish of ejection orifice formation

Engineering Contradiction:
Improvechip areaVSAvoidejection orifice formation quality
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

Different regions of the reticle are used for different exposure steps, with each region optimized for its specific location. This allows the chip area to be maximized by utilizing the full field angle, while maintaining ejection orifice formation quality through location-specific exposure optimization.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent adds a temporal dimension to the exposure process by conducting exposures at different times (first exposure and second exposure). This allows the system to overcome the spatial limitation of lens aberrations by distributing the pattern formation across multiple time points, thereby maintaining quality while maximizing chip area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If exposure is conducted at positions outside the center of the reticle to utilize the full field angle, then productivity is improved by exposing more chips at once, but the position of the ejection orifice deviates from the center

Engineering Contradiction:
Improvenumber of chips exposed simultaneouslyVSAvoidejection orifice position accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The exposure process is segmented into multiple steps, with each step using a different region of the reticle. This allows the system to utilize the full field angle for higher productivity while maintaining position accuracy by compensating for aberrations through multiple targeted exposures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the exposure parameters (light source position, reticle position, exposure timing) between the first and second exposures. By adjusting these parameters, the system compensates for position deviations caused by using the full field angle, thereby maintaining ejection orifice position accuracy while achieving high productivity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables batch exposure of multiple chips with reduced total pitch differences between ejection orifice arrays, effectively preventing color unevenness and improving production efficiency by maintaining accurate ejection orifice positions, thus enhancing the quality of printed images.

Implementation Method 1

conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed on the substrate... to form ejection orifice array patterns in the photosensitive resin layer

Methodology Applied
Scientific EffectPhotopolymerization: Photopolymerisation

Data Source

PatentUS8945817B2Process for producing chip
Publication Date: 2015.02.03 CANON KK
  • US8945817B2 patent drawing
  • US8945817B2 patent drawing
  • US8945817B2 patent drawing

AI summary

A process for producing a chip in which plural ejection orifice arrays are arranged including conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed thereon while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the resin layer, developing the patterns to form ejection orifice arrays in the resin layer, and dividing the wafer to form plural chips in which the plural ejection orifice arrays are arranged. The exposure is conducted once to form in the resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip.