Inkjet Head Multilayer Interconnect for High-Density Channel Rows
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Solution Overview
Problem
Existing inkjet heads with multiple rows of channels face challenges in making electrical connections between drive electrodes and drive circuits, particularly when channels are densely packed, as it becomes difficult to draw out interconnection electrodes without short circuits or open circuits, and the process is complicated by the need to connect FPCs on both surfaces of the head chip.
Innovation Solution
The design features a multilayer member with lead wirings for each row of channels, where the lead wiring for one row extends beyond the edge of the head chip, allowing for easy connection to the drive circuit at one edge part and avoiding the complexity of connecting FPCs from opposite surfaces, using a multilayer structure with insulating layers and penetrating electrodes to ensure electrical contact without short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If interconnection electrodes are drawn out from channels to the edge part of the head chip in high-density multi-row channel construction, then electrical connection accuracy is improved, but the risk of short circuits and open circuits increases due to narrow gaps between channels
Solution Approach 1:
The patent introduces an intermediary substrate that receives electrical connections from multiple rows of channels through its thickness. This intermediary acts as a mediator between the densely packed channels and the final FPC connection, allowing electrodes to be drawn out through the substrate rather than directly across narrow channel gaps, thereby reducing short circuit risk while maintaining connection accuracy
Solution Approach 2:
The patent transitions from planar electrode routing (2D) to three-dimensional routing by drawing electrodes through the thickness of the intermediary substrate. This dimensional change allows electrodes from different channel rows to be connected without crossing narrow gaps on the surface, eliminating short circuit risks while maintaining manufacturing precision
2Adaptability or versatility
If FPCs are connected on both surfaces of the head chip to access multiple channel rows, then electrical connection versatility is improved, but the connection process complexity increases due to needing to flip the head chip
Solution Approach 1:
The patent merges the connection functions for multiple channel rows into a single location on one surface of the intermediary substrate. By routing electrodes from different rows through the substrate to converge at one edge, it combines what would have been separate connection operations on opposite surfaces into a single unified connection process
Solution Approach 2:
The intermediary substrate serves multiple functions: it acts as an electrical interconnection layer, a mechanical support structure, and a routing medium that consolidates multiple electrode paths. This multi-functionality allows all channel rows to be accessed through a single FPC connection point, eliminating the need for dual-surface connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables easy and stable electrical connections for drive signals to multiple rows of channels, simplifying the connection process and maintaining high accuracy and reliability even with high-density channel arrangements, allowing for efficient operation of the inkjet head.
Implementation Method 1
a driving wall made of a piezoelectric member; wherein each of the plurality of channels is provided with an opening on a front surface of the head chip, from which side ink is ejected from the head chip
Data Source
Figure 1
Figure 2a~2b
Figure 3a~3e
AI summary
In a harmonica type head chip (1) having a plurality of rows of channels (row A and row B), connection electrodes for row A and the connection electrodes for row B formed on the back surface of the head chip (1) are connected to a multilayer member (3) having an insulating layer on one surface of which are formed the lead wirings (32A) for row A and on the other surface of which are formed the lead wirings (32B) for row B, and the lead wirings for row B are made to protrude outwards more than the lead wirings for row A and drive interconnections are electrically connected to the lead wirings for row A and the lead wirings for row B.