Ink-Jet Printed Conductive Pads for Post-Stack Semiconductor Testing
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Solution Overview
Problem
Stacked semiconductor device assemblies pose challenges for post-stacking functional testing due to compromised electrical interconnects and incompatibility with lithographic approaches for forming conductive probe pads.
Innovation Solution
Ink-jet printing of conductive probe pads directly on exposed conductive elements or concurrently with ink-jet printed traces, allowing for electrical testing of the assembly post-stacking without damaging the delicate structures like through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic approaches are used to form conductive probe pads, then precise patterning is achieved, but the process is incompatible with post-stacking testing and may damage delicate structures
Solution Approach 1:
The patent replaces lithographic approaches (optical/mechanical system) with direct metal deposition techniques to form conductive probe pads. This substitution allows for post-stacking formation of test pads without requiring complex lithographic processing that would be incompatible with already-assembled devices, while still achieving precise pad formation through controlled deposition methods
Solution Approach 2:
The patent forms conductive probe pads and interconnect structures before final stacking operations. By preparing the test access structures in advance on individual devices or interposers, the system enables subsequent stacking without requiring post-assembly lithographic processing, thus resolving the incompatibility between lithography and post-stacking testing
2Reliability
If conventional packaging processes are used, then dies are protected from environmental factors, but electrical interconnects may be compromised during stacking operations
Solution Approach 1:
The patent implements protective measures beforehand by forming robust conductive interconnect structures with sufficient mechanical strength and compliance characteristics before stacking. These pre-formed interconnects are designed to withstand subsequent stacking operations and encapsulation processes, cushioning the delicate electrical connections from potential damage during assembly
Solution Approach 2:
The patent modifies the physical and mechanical parameters of conductive interconnect structures through controlled deposition processes, creating materials with optimized combinations of electrical conductivity, mechanical strength, and compliance. These parameter changes enable the interconnects to withstand stacking operations while maintaining electrical integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective post-stacking testing of semiconductor device assemblies by providing accessible conductive pads that can be easily formed on stacked devices, ensuring the integrity of electrical interconnects and active circuits.
Implementation Method 1
ink-jet printing of conductive probe pads
Data Source
AI summary
A method for forming a semiconductor device assembly is described. The method comprises vertically stacking at least one semiconductor device over a substrate; and ink-jet printing, after vertically stacking the at least one semiconductor device, a conductive pad on an exposed conductor of the at least one semiconductor device or of the substrate. The method can further include testing an electrical circuit of the semiconductor device assembly by electrically probing the electrical circuit through the conductive pad.