Inkjet Printed Leadframe Using Metallic Nanoinks
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Solution Overview
Problem
Existing leadframe packaging for integrated circuit devices requires thicker metal substrates for structural integrity, leading to increased material costs, especially when using valuable metals like copper, silver, and gold, despite the primary function only needing thinner interconnects.
Innovation Solution
The use of an inkjet printer to create ultra-thin electrical interconnect patterns using metallic nanoinks on a thin substrate, which can be adapted for high-temperature processing and later removed, allowing for precise control of thickness and reduced material usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thicker metal substrates are used for leadframes, then structural integrity is improved, but material costs increase due to increased use of valuable metals like copper, silver, and gold
Solution Approach 1:
The patent applies this principle by transitioning from traditional thick rigid metal substrates to thin flexible metal foil substrates. The thin foil substrates (ranging from 1 to 25 micrometers thick) provide the necessary structural integrity for leadframe applications while dramatically reducing metal consumption. The flexibility of the thin foil allows it to be formed into required shapes and provides sufficient mechanical strength through proper substrate selection and design, thereby resolving the contradiction between structural integrity and material usage.
2Quantity of substance
If thinner metal substrates are used for leadframes, then material costs are reduced, but structural integrity deteriorates
Solution Approach 1:
The patent applies this principle by changing the thickness parameter of the metal substrate to ultra-thin dimensions (1-25 micrometers) while compensating for the reduced thickness through careful selection of substrate materials with appropriate mechanical properties. The parameter change in thickness is offset by optimizing other parameters such as material composition, foil structure, and dimensional specifications to maintain adequate structural integrity for leadframe functionality.
3Ease of manufacture
If traditional etching processes are used to create electrical interconnect patterns, then manufacturing simplicity is maintained, but material waste increases due to the need for thicker panels
Solution Approach 1:
The patent applies this principle by replacing traditional thick metal panels with thin flexible metal foil substrates. This transition enables the use of advanced patterning techniques that can create precise electrical interconnect patterns with minimal material waste. The thin foil substrate allows for more efficient material utilization during the patterning process, reducing the amount of metal that needs to be removed or wasted compared to traditional thick panel etching methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly thinner leadframes with reduced material costs, achieving structural integrity while minimizing the use of expensive metals, and enabling efficient packaging of integrated circuit devices.
Implementation Method 1
an inkjet printer to print metallic nanoinks to a thin substrate
Data Source
AI summary
Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.