Inkjet Printhead Transistor Driver with Thin Gate Oxide
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Solution Overview
Problem
Conventional inkjet printhead chips face challenges in reducing their area while maintaining performance and preventing error operations, particularly in integrating drivers and heating devices effectively.
Innovation Solution
The design incorporates a substrate with transistors, an isolation structure, a dielectric layer, and conductor sections, where the gate oxide layer is thinner than 800 Å, allowing for higher electric fields and increased drive current, and a resistive layer with heating areas that reduce resistance and power density, along with a passivation layer to prevent corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate oxide layer thickness is reduced to less than 800 Å, then the drive current increases and area is reduced, but the risk of error operation and susceptibility to impurities increases
Solution Approach 1:
The patent changes the physical parameter of gate oxide layer thickness to less than 800 Å, which enables higher drive current and reduced area while maintaining device functionality through controlled parameter optimization
Solution Approach 2:
The patent introduces a passivation layer as an intermediary protective structure between the environment and the transistor components, preventing impurity contamination and error operations while allowing the thin gate oxide structure to function
2Adaptability or versatility
If drivers and heating devices are integrated onto the inkjet printhead chip, then device functionality is improved, but the chip area increases
Solution Approach 1:
The patent merges the driver circuit and heating device functions onto a single inkjet printhead chip, integrating multiple functionalities into one compact device to improve versatility while controlling area through efficient layout
Solution Approach 2:
The patent utilizes vertical layering (different dimensions) to accommodate multiple functional components - transistors in one layer, heating elements in another, and passivation layers above, effectively packing integrated functionality without proportionally increasing planar area
3Reliability
If the heating device resistance is reduced to less than 95 ohm with power density less than 2 GW/m2, then manufacturing cost is reduced and reliability is improved, but the heating efficiency decreases
Solution Approach 1:
The patent optimizes the heating device parameters by controlling resistance to less than 95 ohm and power density to less than 2 GW/m2, achieving a balance between reliability, manufacturing cost, and acceptable heating efficiency through parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a smaller layout area for the same driving capability, reduces manufacturing costs, and maintains a planar surface while preventing impurities from affecting the device structures.
Implementation Method 1
the gate oxide layer is thinner than 800 Å, allowing for higher electric fields and increased drive current
Implementation Method 2
a resistive layer with heating areas that reduce resistance and power density
Implementation Method 3
In the piezoelectric jetting technique, the actuator is a piezoelectric material layer. When a voltage is applied to the piezoelectric material, the piezoelectric layer deforms to pressurize the ink within an ink chamber so that a jet of ink is forced out from the ink chamber via an ink nozzle.
Implementation Method 4
In the thermal bubble jetting technique, a small quantity of ink is rapidly vaporized by a heater (resistor) to generate a sudden increase of pressure in the ink so that a droplet of ink is squeezed out from an ink chamber via an ink nozzle.
Data Source
AI summary
An inkjet printhead chip includes a substrate, transistors, isolation structures, a dielectric layer, a resistive layer and conductive sections. Each transistor includes a gate, a source, a drain and a gate oxide disposed between the gate and the substrate. The isolation structures are on the substrate surface and isolate the transistors. The dielectric layer covers the transistors and the isolation structures, and has openings exposed the source and the drain. Several heating regions are in the resistive layer that is on the dielectric layer. In the conductive sections, the first conductive section is on the resistive layer and exposes the heating regions for forming several heating devices. Each heating device has resistance less than 95 ohm and power density less than 2 GW/m2; the second conductive section and the third conductive section are electrically coupled to the drain and the source through the openings of the dielectric layer respectively.