Inline Buffer for In-Memory Post Package Repair
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Solution Overview
Problem
Current memory systems face challenges in efficiently implementing soft Post Package Repair (PPR) due to a lack of temporary storage space, which hinders the effective mapping of failed rows to spare rows without requiring system reboots or extensive memory controller involvement.
Innovation Solution
Incorporating an internal temporary storage mechanism, such as an inline prefetch buffer or scratchpad memory within the memory device, to locally transfer data from failed rows to spare rows, reducing the need for external memory controller intervention and enabling quicker, temporary repair of failed rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sPPR implementation is used where the memory controller reads and temporarily stores all data from the failed row, then the failed row can be mapped to a spare row, but the memory controller becomes heavily involved and the process becomes complex and time-consuming
Solution Approach 1:
The patent extracts the temporary storage function from the memory controller and places it directly within the memory device. The memory device now contains its own internal buffer (such as a prefetch buffer or scratchpad memory) to temporarily hold data from failed rows, eliminating the need for the memory controller to read and store data externally. This reduces memory controller involvement and simplifies the overall system architecture.
Solution Approach 2:
The memory device performs the repair operation autonomously using its own internal resources. When a row failure is detected, the memory device automatically transfers data from the failed row to an internal buffer, maps the failed row to a spare row, and then restores data from the buffer to the spare row - all without requiring memory controller intervention for data transfer, thereby enabling self-service repair.
2Reliability
If the memory controller reads and stores all data from the failed row externally, then repair can be performed, but the process becomes slower and requires system reboot or extensive controller intervention
Solution Approach 1:
The memory device maintains an internal buffer that can temporarily hold row data in advance. When a failure is detected, the data is already available within the device's internal buffer, eliminating the time required for external read and transfer operations. This preliminary preparation of data storage capability within the device significantly reduces repair time.
Solution Approach 2:
The autonomous repair process within the memory device eliminates the need for system reboot or extensive memory controller intervention. The memory device independently performs data transfer, row mapping, and data restoration operations using its internal buffer, dramatically reducing the time loss associated with traditional external repair methods.
3Ease of manufacture
If no internal temporary storage is provided in the memory device, then the device structure remains simple, but effective soft PPR cannot be implemented without extensive external controller involvement
Solution Approach 1:
The patent utilizes existing memory device structures (prefetch buffers or scratchpad memory) for dual purposes: their original function plus temporary storage for PPR operations. This multi-functional approach enables soft PPR capability without adding completely new dedicated storage structures, maintaining manufacturing simplicity while enhancing adaptability.
Solution Approach 2:
By providing internal temporary storage within the memory device, the system enables autonomous soft PPR capability. The memory device can independently perform repair operations without extensive external controller involvement, achieving both structural simplicity and enhanced versatility through self-service repair functionality.
Data Source
AI summary
In a memory system, a memory device has a memory array with multiple rows of memory having logical addresses mapped to their physical addresses and at least one spare row not having a logical address mapped to its physical address. A controller detects a failure of one of the multiple rows of memory (“failure row”) and executes a post package repair (PPR) mode. The controller can be internal to the memory device or external to the memory device. The memory device includes an internal scratchpad to allow transfer of data contents from the failure row to the spare row. The controller can map the logical address of the failure row from the physical address of the failure row to the physical address of the spare row, transfer data contents from the failure row to the internal scratchpad, and transfer the data contents from the internal scratchpad to the spare row.