Memory Inline Cipher Engine With On-Chip Integrity and Anti-Replay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Off-chip encryption in AI/ML accelerators lacks high security and is costly, with existing systems requiring an interface between the SOC and DRAM, leading to vulnerabilities and increased power consumption.
Innovation Solution
Implement a system on chip (SOC) with a secure processing unit, AI/ML accelerator, inline cypher engine, IOMMU, MPU, and CPU, utilizing on-chip integrity trees and AES encryption to enhance security and reduce power consumption by performing encryption and integrity checks on-chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If off-chip encryption is used with DRAM interface, then encryption functionality is achieved, but security is reduced and power consumption is increased
Solution Approach 1:
The patent merges the encryption engine directly into the memory chip structure, combining storage and encryption functions in a single integrated component. This eliminates the need for separate off-chip encryption operations and DRAM interfaces, thereby reducing power consumption while maintaining or enhancing security through on-chip processing.
Solution Approach 2:
The patent extracts the encryption functionality from the traditional off-chip processing model and relocates it directly into the memory chip. By taking out the encryption engine from external processing and embedding it within the memory structure, the system achieves both lower power consumption and improved security through dedicated hardware acceleration.
2Reliability
If off-chip encryption is used, then encryption functionality is achieved, but system cost is increased
Solution Approach 1:
The patent combines multiple functions (storage, encryption, and decryption) into a single integrated memory chip structure. This merging eliminates the need for separate encryption hardware components and reduces overall system complexity, thereby lowering manufacturing costs while maintaining high security through integrated design.
Solution Approach 2:
The patent creates a multi-functional memory chip that serves as both storage medium and encryption engine. This universal component performs multiple functions (data storage, encryption, decryption, and integrity verification) that would traditionally require separate components, reducing system cost while enhancing security through consolidated functionality.
3Reliability
If on-chip encryption is implemented, then security is enhanced and power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges encryption and storage functions into a single integrated chip, which simplifies the overall system architecture by eliminating the need for separate encryption hardware and complex interconnections. Although the individual chip is more complex, the system-level integration reduces overall complexity and improves security through dedicated on-chip processing.
Data Source
AI summary
A system on chip includes a secure processing unit (SPU), an artificial intelligence/machine learning accelerator (AI/ML accelerator), a memory inline cypher engine, and a central processing unit (CPU). The SPU is used to store biometrics of users. The AI/ML accelerator is used to process images, and analyze the biometrics of users. The AI/ML accelerator includes a micro control unit (MCU) for intelligently linking access identifications (IDs) to version numbers (VNs). The memory inline cypher engine is coupled to the AI/ML accelerator and the SPU for receiving a register file from the MCU, encrypting data received from the AI/ML accelerator, and comparing the biometrics of the users received from the SPU with the data. The CPU is coupled to the SPU and the AI/ML accelerator for controlling the SPU and the AI/ML accelerator.