Inline Contactless Metrology Chamber for Wafer Sheet Resistance
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Solution Overview
Problem
Current wafer metrology systems in semiconductor fabrication are costly and inefficient, requiring separate inspection stations and slowing down wafer throughput, while existing technologies lack effective methods for inline, contactless measurement of sheet resistance and other parameters in harsh fabrication environments.
Innovation Solution
An inline contactless metrology system using eddy current sensors integrated into the IC fabrication tool, allowing for non-contact measurement of sheet resistance and other parameters in a wafer's process layers, enabling real-time monitoring and control during processing stages without disrupting the fabrication flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate metrology stations are used for wafer inspection, then measurement capabilities are provided, but wafer throughput is slowed down and manufacturing costs increase
Solution Approach 1:
The patent combines the metrology measurement function with the existing fabrication chamber by integrating a sensor assembly that can measure wafer parameters (such as sheet resistance via eddy currents) while the wafer remains in the fabrication chamber. This eliminates the need to transport wafers to separate metrology stations, thereby maintaining measurement capabilities while preserving continuous fabrication flow and wafer throughput.
2Reliability
If contactless measurement is implemented, then wafer handling is improved and contamination is reduced, but measurement capability in harsh fabrication environments is limited
Solution Approach 1:
The patent replaces mechanical contact-based measurement methods with contactless eddy current sensing. The sensor assembly uses electromagnetic fields to measure wafer parameters without physical contact, eliminating contamination risks and handling issues while enabling measurements to be performed directly within the harsh fabrication chamber environment where mechanical probes would fail or contaminate the wafer.
3Extent of automation
If inline metrology is implemented, then real-time process control is achieved, but device complexity and initial costs increase
Solution Approach 1:
The patent designs the sensor assembly to serve multiple functions: it can measure different wafer parameters (sheet resistance, thickness, material composition) using eddy current principles, and it can be integrated into various fabrication chamber types. This multi-functionality reduces overall system complexity compared to having separate specialized measurement devices, as one universal sensor system replaces multiple single-purpose measurement tools.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances productivity by reducing costs and wafer wastage, improving yield control, and enabling real-time error detection and correction, thus optimizing the semiconductor manufacturing process.
Implementation Method 1
a contactless sensor assembly for sensing sheet resistance of a process layer of the semiconductor wafer based on eddy currents generated in the process layer
Implementation Method 2
at least one sensor probe operative for sensing sheet resistance of the process layer
Data Source
AI summary
An integrated circuit (IC) fabrication tool and associated method for facilitating inline contactless sheet resistance measurement. In one arrangement, the tool comprises at least one main chamber, one or more processing chambers detachably coupled to the main chamber, each of the one or more processing chambers configured for effectuating a respective processing operation on a semiconductor wafer, and at least one sensor chamber detachably coupled to the at least one main chamber, the at least one sensor chamber having a contactless sensor assembly for sensing sheet resistance of a process layer of the semiconductor wafer based on eddy currents generated in the process layer.