Inline Downscaling Hardware for Video Encoding Latency

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Solution Overview

Problem

Ultra-low latency video encoding networks face significant latency issues due to the need for full resolution passes, which increase computational load and power consumption, especially during scene changes, and conventional external downscaling methods further exacerbate these problems.

Innovation Solution

Implementing inline downscaling hardware within the encoder pipeline to perform on-the-fly downsampling of video frames, reducing the computational load and power consumption by downsampling frames internally without the need for external memory, and using dedicated hardware to convert between different color subsampling schemes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If full resolution passes are used for video encoding, then encoding quality is improved, but latency and computational load increase significantly

Engineering Contradiction:
Improveencoding qualityVSAvoidlatency
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The encoding process is divided into two distinct passes: a first pass at reduced resolution to gather statistics, and a second pass at full resolution to encode final frames. This segmentation allows the system to separate quality-critical operations from speed-critical operations, reducing overall latency while maintaining encoding quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Statistics such as quantization parameters and motion complexity are pre-calculated during a first pass at reduced resolution before the actual full-resolution encoding begins. This preliminary action prepares encoding parameters in advance, enabling faster full-resolution encoding without sacrificing quality.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If full resolution passes are used for video encoding, then encoding quality is improved, but power consumption increases

Engineering Contradiction:
Improveencoding qualityVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by stationary object

Solution Approach 1:

The encoding workload is segmented into a low-power first pass at reduced resolution and a focused second pass at full resolution. By performing statistics gathering at lower resolution, the system significantly reduces the computational power required for the initial analysis phase.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first pass uses partial resolution (reduced quality) to gather sufficient statistics for encoding, which is excessive for final quality but necessary for speed. This partial action at reduced resolution reduces power consumption while still providing adequate data for the second pass.

Inventive Principle:
Principle #16Partial or excessive action

3Volume of moving object

If external downscaling methods are used, then frame size is reduced, but device complexity and memory requirements increase

Engineering Contradiction:
Improveframe sizeVSAvoidsystem complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The downscaling function is merged directly into the encoder pipeline as an integrated component. Rather than using separate external downscaling hardware or software, the encoder incorporates downscaling capabilities internally, reducing system complexity and eliminating the need for external memory interfaces.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The encoder is designed with multi-functionality, combining both encoding and downscaling operations within a single device. This universal design eliminates the need for separate downscaling hardware and reduces overall system complexity while maintaining the ability to reduce frame size efficiently.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230097092A1Method and system of video coding with inline downscaling hardware
Publication Date: 2023.03.30 INTEL CORP
  • US20230097092A1 patent drawing
  • US20230097092A1 patent drawing
  • US20230097092A1 patent drawing

AI summary

Techniques related to video encoding include inline downscaling hardware in multi-pass encoding.