In-Line ECC Memory Bridge for Address Fault Protection
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Solution Overview
Problem
Data stored in memory devices, such as DRAM or DDR SDRAM, is prone to errors due to physical damage, particle strikes, or logical bugs, which can lead to incorrect system operation, particularly in critical applications requiring functional safety.
Innovation Solution
An integrated circuit with an interconnect and bridge that performs error-correcting code (ECC) calculations and address translation, caching ECC data, and implementing read-modify-write operations to ensure data integrity across bursts, using a novel address translation scheme to protect against address faults and minimize memory waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC data is stored in separate memory locations, then data integrity is improved, but memory address management complexity increases and memory space efficiency deteriorates
Solution Approach 1:
The patent combines ECC data and regular data into a single contiguous memory block, eliminating the need for separate address management for ECC data. The bridge device performs address translation that automatically maps system addresses to the unified memory structure, reducing address management complexity while maintaining data integrity through integrated ECC protection.
Solution Approach 2:
The unified memory structure serves multiple functions: it stores both user data and ECC data, handles address translation, and provides error correction capabilities. This multi-functional approach eliminates the need for separate dedicated ECC memory regions, simplifying address management while maintaining reliability.
2Reliability
If traditional ECC implementation is used, then error correction capability is provided, but memory space efficiency deteriorates due to separate ECC storage
Solution Approach 1:
By merging ECC data and user data into a single contiguous memory block, the patent optimizes memory space utilization. The unified structure eliminates gaps and separate allocations, allowing more efficient packing of data and ECC information within the same memory capacity.
3Reliability
If address translation is implemented, then protection against address faults is improved, but processing overhead increases
Solution Approach 1:
The bridge device performs address translation in advance as part of the memory access operation, converting system addresses to physical memory addresses before data access occurs. This preliminary address translation prevents address faults before they can affect data integrity, while the translation is integrated into the normal memory access flow to minimize processing overhead.
4Reliability
If in-line ECC protection is implemented, then data coherence is improved, but device complexity increases
Solution Approach 1:
The bridge device acts as an intermediary between the system and the unified memory structure, handling ECC calculations, address translations, and data coherence management. By placing the bridge at this intermediate level, the patent maintains data coherence through integrated ECC protection while isolating the complexity within the bridge device rather than distributing it throughout the entire memory system.
Data Source
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AI summary
A memory system (100) having an interconnect (101) configured to receive commands from a system (107) to read data from and/or write data to a memory device (106). The memory system (100) also has a bridge (102) configured to receive the commands from the interconnect (101), to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge (102) may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.