Inline ECC Function for System-on-Chip Networks
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Solution Overview
Problem
Traditional error-correcting code (ECC) protection for dynamic random access memory (DRAM) is costly due to the need for additional components and interface pins, and bus structures in system-on-chip (SoC) integrated circuits can lead to signaling problems with increased integration, making them unsuitable for efficient data communication.
Innovation Solution
An inline error-correcting code (ECC) function integrated into a network-on-chip (NoC) system, which computes ECC data for read and write transactions and provides them to the memory controller, eliminating the need for additional ECC components on DRAM and allowing flexible storage of ECC data, thereby decoupling the DRAM controller from the ECC function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional out-of-band ECC protection is implemented, then memory data protection is achieved, but additional DRAM components and interface IO pins are required, increasing cost
Solution Approach 1:
The patent merges the ECC function with the NoC switch, integrating error correction capabilities directly into the network infrastructure. The NoC switch now performs both data routing and ECC computation/verification, eliminating the need for separate ECC components and reducing interface complexity.
Solution Approach 2:
The NoC switch is designed to perform multiple functions: data packet routing, ECC computation for write transactions, and ECC verification for read transactions. This multi-functionality eliminates the need for dedicated ECC hardware components while maintaining comprehensive memory protection.
2Device complexity
If bus structure is used for data communication in SoC, then simple architecture is maintained, but signaling problems occur with increased circuit integration
Solution Approach 1:
The patent segments the monolithic bus structure into a distributed NoC architecture with multiple switches and point-to-point connections. This segmentation allows data to be routed through multiple smaller, manageable segments rather than a single complex bus, reducing signaling problems while maintaining architectural simplicity at each node.
Solution Approach 2:
The NoC switches act as intermediaries between master devices and memory controllers, replacing direct bus connections. These intermediary switches manage data flow, perform ECC operations, and route packets, eliminating the signaling conflicts that would occur in a high-integration direct bus architecture.
3Device complexity
If ECC function is integrated into NoC, then additional ECC components on DRAM are eliminated, but inline ECC computation must be performed for each transaction
Solution Approach 1:
The NoC switch performs ECC computation in advance during write transactions, calculating and storing ECC data before the actual memory write occurs. This preliminary action ensures that ECC protection is already in place when data is written, eliminating the need for separate ECC processing steps.
Solution Approach 2:
The NoC switch serves itself by performing both routing and ECC functions within the same hardware unit. The switch automatically computes ECC for outgoing writes and verifies ECC for incoming reads without requiring external ECC components, making the system self-sufficient and reducing overall complexity.
Data Source
AI summary
An example integrated circuit (IC) includes a network-on-chip (NoC), a master device coupled to the NoC, a memory controller coupled to the NoC configured to control a memory coupled to the IC, and an inline error-correcting code (ECC) circuit coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.