Inline Encryption Engine Pipeline Latency Management

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Solution Overview

Problem

Existing systems face challenges in efficiently and transparently encrypting and decrypting data stored in memory, particularly in external memory like DDR, which can be vulnerable to unauthorized access, and incur latency when encrypting or decrypting data.

Innovation Solution

An inline encryption engine within a memory controller that includes multiple pipelines for encrypted and plaintext data, with control logic to manage output and cryptographic key management, allowing for fast inline encryption and decryption while maintaining data integrity and transparency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If inline encryption/decryption is implemented in memory controller, then data security is improved, but processing latency increases

Engineering Contradiction:
Improvedata securityVSAvoidprocessing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The encryption/decryption process is divided into multiple pipelines (first pipeline for encrypted data, second pipeline for plaintext data) that operate in parallel. Each pipeline handles specific data types independently, allowing simultaneous processing and reducing overall latency while maintaining security.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system pre-loads encryption keys into the memory controller before data processing begins. This preliminary key loading eliminates the need for key retrieval during data encryption/decryption operations, reducing processing time and latency.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple pipelines are used for encryption and plaintext data, then processing speed is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidpipeline management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A multiplexer acts as an intermediary component that simplifies the complexity of managing multiple pipelines. The multiplexer selectively switches between outputs of the first pipeline (encrypted data) and second pipeline (plaintext data), providing a unified output interface while maintaining parallel processing capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The control logic dynamically adjusts which pipeline's output is selected based on data availability and processing requirements. This dynamic switching allows the system to adapt to varying data types and processing speeds, optimizing performance while managing complexity through flexible control rather than fixed architecture.

Inventive Principle:
Principle #15Dynamics

3Productivity

If fast data passes slow data in pipeline, then throughput is improved, but data collision risk increases

Engineering Contradiction:
ImprovethroughputVSAvoiddata collision risk
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system segments data into distinct encrypted and plaintext pipelines, preventing mixing of data types. This segmentation eliminates collision risks between different data types while allowing each pipeline to operate at its optimal speed independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multiplexer serves as an intermediary that coordinates output from both pipelines, ensuring that data from either pipeline is selected appropriately based on validity flags and processing requirements. This intermediary control prevents data collisions at the output stage while maintaining high throughput from both pipelines.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4216096B1Processing pipeline where fast data passes slow data
Publication Date: 2024.09.11 NXP BV
  • EP4216096B1 patent drawingFigure 1
  • EP4216096B1 patent drawingFigure 2
  • EP4216096B1 patent drawingFigure 3

AI summary

Various embodiments relate to an inline encryption engine in a memory controller configured to process data read from a memory, including: a first data pipeline configured to receive data that is plaintext data and a first validity flag; a second data pipeline having the same length as the first data pipeline configured to: receive data that is encrypted data and a second validity flag; decrypt the encrypted data from the memory and output decrypted plaintext data; an output multiplexer configured to select and output data from either the first pipeline or the second pipeline; and control logic configured to control the output multiplexer, wherein the control logic is configured to output valid data from the first pipeline when the second pipeline does not have valid output decrypted plaintext data available.