Inline Error Correction Logic for Memory Devices
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Solution Overview
Problem
As memory devices shrink, they become more prone to data errors, leading to increased error rates, and existing error detection and correction techniques at the memory controller increase memory access latency by requiring additional computations after data is received.
Innovation Solution
Implementing an inline error detection and correction mechanism within the memory device, where data and error correction codes are read in parallel and processed concurrently as data is transferred over a serial link to the memory controller, allowing error detection and correction without adding to normal data access latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction is performed at the memory controller after data is received, then data correctness is ensured, but memory access latency increases due to additional computations
Solution Approach 1:
The patent performs error detection and correction computations inline within the memory device during the data read process, before the data is transferred to the memory controller. The error correction code is generated and applied concurrently with data retrieval, so that by the time data reaches the memory controller, error correction is already complete, eliminating additional latency at the controller.
Solution Approach 2:
The patent moves the error detection and correction functionality from the memory controller dimension to the memory device dimension. By implementing error correction logic within the memory device itself rather than at the controller, the system changes where the computational workload occurs, allowing parallel processing that doesn't block the data transfer path.
2Quantity of substance
If memory devices shrink to increase storage capacity, then storage density improves, but data error rates increase making devices more prone to errors
Solution Approach 1:
The memory device performs error detection and correction on its own internally, without requiring external intervention from the memory controller. The inline error correction logic is integrated within the memory device, allowing it to self-correct errors that arise from shrinking dimensions and increased error susceptibility.
3Reliability
If error correction codes are always transmitted with data, then data correctness is ensured, but bandwidth consumption increases
Solution Approach 1:
The patent extracts the error correction computation from the data transfer path and performs it separately within the memory device. The error correction code is generated and applied internally, and only the corrected data is transmitted to the memory controller, rather than transmitting both data and error correction codes separately.
Data Source
AI summary
Data is read from memory cells in the memory device. The read data is transferred over a link to a memory controller that is external of the memory device. While the transferring of the read data is ongoing, error detection of the read data is performed inside the memory device using an error correction code.