Inline Hardware Conversion Units for HDR to SDR Format Transition
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Solution Overview
Problem
Conventional HDR/WCG to SDR/SCG conversion processes in display devices are performance-intensive due to software shaders, leading to increased memory bandwidth usage and power consumption, which degrades gaming performance and overall rendering efficiency.
Innovation Solution
Implementing inline hardware conversion units that perform the conversion process independently of memory access, using a unified encoding and decoding unit to transition between HDR/WCG and SDR/SCG formats without software components, thereby reducing memory access and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software shaders are used to perform HDR/WCG to SDR/SCG conversion, then conversion functionality is achieved, but memory bandwidth usage increases and power consumption increases
Solution Approach 1:
The patent replaces software-based shader processing with dedicated hardware conversion circuits. The hardware converter performs HDR/WCG to SDR/SCG conversion through specialized electronic circuits that directly process pixel data without requiring software execution, thereby eliminating the high power consumption associated with software shaders while maintaining full conversion functionality.
Solution Approach 2:
The patent introduces a hardware converter as an intermediary component between the graphics processing unit and the display output. This dedicated hardware module serves as a mediator that handles the format conversion task, isolating it from the main GPU processing pipeline and preventing it from consuming GPU power resources, thus reducing overall system power consumption while preserving conversion capabilities.
2Adaptability or versatility
If software shaders are used to perform HDR/WCG to SDR/SCG conversion, then conversion functionality is achieved, but memory bandwidth usage increases
Solution Approach 1:
The patent replaces software shader processing with hardware conversion circuits that perform format conversion using dedicated electronic pathways. These hardware circuits process pixel data directly through logic gates and arithmetic units, eliminating the need for repeated memory reads and writes that occur during software shader execution, thereby significantly reducing memory bandwidth consumption while maintaining full conversion functionality.
Solution Approach 2:
The patent segments the graphics rendering pipeline by extracting the format conversion function into a separate hardware module. This segmentation allows the main GPU to focus on rendering tasks while the dedicated hardware converter handles format conversion independently with its own data pathways, preventing conversion operations from competing for memory bandwidth with other GPU operations.
3Adaptability or versatility
If multiple memory accesses are performed during conversion process, then conversion is completed, but rendering speed decreases
Solution Approach 1:
The patent replaces software-based conversion with hardware circuits that perform format conversion in a single pass through the pixel data stream. The hardware converter uses parallel processing architectures with multiple conversion units operating simultaneously, completing the entire HDR/WCG to SDR/SCG conversion process in one hardware stage without requiring multiple memory access cycles, thereby maintaining rendering speed while ensuring conversion completion.
Solution Approach 2:
The patent implements continuous format conversion processing through a pipelined hardware architecture. As pixel data flows continuously through the conversion pipeline, each stage processes data without interruption or memory access delays. This continuous action ensures that conversion is completed for all pixels while maintaining the overall rendering throughput and speed, eliminating the stop-start nature of software-based processing.
Data Source
AI summary
A device includes an encoder, decoder, codec or combination thereof and inline hardware conversion units that are operative to convert stored image data into one of: an HDR/WCG format and an SDR/SCG format during the conversion process. Each of the inline hardware conversion units is operative to perform the conversion process independent of another read operation with the memory that stores the image data to be converted. In one example, an encoding unit is operative to perform a write operation with a memory to store the converted image data after completing the conversion process. In another example, a decoding unit is operative to perform a read operation with the memory to retrieve the image data from the memory before initiating the conversion process. In another example, an encoder/decoder unit is operative to perform at least one of: the read operation and the write operation.


