In-Loop Filtering Acceleration Circuit for Video Codec Systems
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Solution Overview
Problem
Video codec systems face significant processing burdens due to the high computational demands of motion estimation and de-blocking filtering, and conventional hardware circuits waste memory bandwidth by repeatedly accessing external memory for macroblock data.
Innovation Solution
A motion estimation acceleration circuit and an in-loop filtering acceleration circuit are introduced, utilizing data from overlapping neighboring macroblocks to reduce memory bandwidth. The motion estimation circuit predicts a start searching point and dynamically adjusts line segments to find the best candidate pixel, while the in-loop filtering circuit performs filtering on reconstructed macroblocks using one-dimensional filters selected based on boundary strength, dividing blocks into 8x8 and 4x4 sections and processing edges according to predefined orders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hardware circuits are used for motion estimation and de-blocking filtering, then the processing function is provided, but memory bandwidth is wasted due to repeated external memory access
Solution Approach 1:
The patent applies preliminary action by pre-storing macroblock data in the buffer memory before motion estimation and de-blocking filtering operations are needed. This allows the acceleration circuits to access previously stored data locally rather than repeatedly accessing external memory, thus reducing memory bandwidth consumption while maintaining processing efficiency
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between external memory and the acceleration circuits. This buffer memory stores macroblock data and serves as a local data source for motion estimation and de-blocking filtering operations, eliminating the need for repeated external memory access and reducing memory bandwidth usage
2Device complexity
If motion estimation and de-blocking filtering are performed by software only, then device complexity is reduced, but processing unit burden increases significantly
Solution Approach 1:
The patent segments the video processing function into distinct hardware acceleration circuits for motion estimation and de-blocking filtering operations. This segmentation allows specific computationally intensive tasks to be handled by dedicated hardware circuits, reducing the processing burden on the general-purpose processing unit while maintaining overall system functionality
Solution Approach 2:
The patent replaces software-based processing with hardware-based acceleration circuits for motion estimation and de-blocking filtering. This substitution uses dedicated electronic circuits to perform calculations that would otherwise require significant software processing power, thereby reducing the processing unit burden while maintaining device complexity at an acceptable level
3Reliability
If external memory is accessed repeatedly for macroblock data, then data availability is ensured, but memory bandwidth is wasted
Solution Approach 1:
The patent applies preliminary action by pre-loading and storing macroblock data in the buffer memory before it is needed for processing. This ensures that data is readily available in local memory when the acceleration circuits need to access it, eliminating the need for repeated external memory access while maintaining data availability
Solution Approach 2:
The buffer memory acts as an intermediary data storage layer between external memory and the processing circuits. It stores macroblock data locally, ensuring reliable data availability for processing operations while preventing repeated access to external memory, thus conserving memory bandwidth
Data Source
AI summary
An in-loop filtering acceleration circuit applied in a video codec system supporting the H.264 standard and the VC-1 standard is provided. The circuit includes multiple one-dimensional (1D) filters configured to perform a filtering process; and a filter selection unit configured to select one of the 1D filters according to the value of the boundary strength to perform the filtering processing to the reconstructed macroblock. The in-loop filtering acceleration circuit further divides the reconstructed macroblock into multiple 8×8 blocks and multiple 4×4 blocks, performs the filtering process to horizontal edges of the 8×8 blocks the reconstructed macroblock row by row from bottom to top, and performs the filtering process to horizontal edges of the 4×4 blocks row by row from top to bottom.